AMD Zen 6 Technical Deep Dive 80

AMD Zen 6 Technical Deep Dive

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EPYC Embedded 9006

Alongside the server launch, AMD announced the EPYC Embedded 9006 Series SP7. Tarang Shah, senior product manager for the EPYC Embedded x86 portfolio, noted that this is the first time AMD has launched an embedded EPYC product alongside the commercial server part rather than months behind it.


The target applications are semiconductor automated test equipment, high-end firewalls and enterprise storage controllers. All three are seeing the same pressure: AI infrastructure growth means faster memory and I/O devices to validate, more network traffic to inspect, and more data to move and process.

For test equipment in particular, the PCIe Gen 6 and CXL 3.1 support is the entire point. You cannot validate Gen 6 SSDs at full speed on a Gen 5 host, and until now there was no x86 server CPU that could do it.

Specifications


The embedded parts share the Venice SP7 silicon and platform: Zen 6 architecture, up to 256 cores, 16 channels of DDR5 with RDIMM and MRDIMM support, 96 lanes of PCIe Gen 6 and CXL 3.1. All SKUs support the full memory channel and PCIe lane count, which is unusual and useful—embedded designs often need the I/O more than the cores.



ModelCoreCores / ThreadsL3 per CorePower LimitBase ClockBoost ClockL3 Cache
9976Zen 6c256 / 5124 MB600 W2.55 GHz4.1 GHz1024 MB
9946Zen 6c192 / 3844 MB600 W3.05 GHz4.1 GHz768 MB
9846Zen 6c168 / 3364.57 MB500 W2.9 GHz4.1 GHz768 MB
9756Zen 6c128 / 2564 MB500 W3.20 GHz4.10 GHz512 MB
9656Zen 6c96 / 1925.33 MB400 W2.85 GHz4.1 GHz512 MB
9556Zen 664 / 1283 MB400 W3.6 GHz5.1 GHz192 MB

The 4.10 GHz ceiling across the top five models marks them as Zen 6c. The cache totals are consistent with whole CCD32s, 1024 MB being eight, 768 MB six and 512 MB four, but AMD also ships CCD32s with half the L3 disabled, as the SP8 9736 on the SKU page shows, so the 168-core part could be six dies at 28 cores or eight at 21, the 96-core part four at 24 or eight at 12, and the cache per core is the only thing the table settles. The 9556 is the outlier, with a 5.1 GHz boost that puts it in Zen 6 territory, and 192 MB of L3 that only adds up one way: eight 12-core dies with 8 cores and half the cache enabled on each. Its server namesake in our CPU database is a different chip altogether, 64 Zen 6c cores at 4.3 GHz with 384 MB of L3 and a 300 W limit.

Performance and Availability


AMD claims up to 1.8x the socket throughput of the EPYC Embedded 9005 series on SPECrate 2017_int_base, and 2.0x the performance of a comparable Intel Xeon 6 processor. On the workloads that matter to the target markets, it claims 1.3x on DPDK L3 forwarding, 1.5x on ISA-L storage algorithms, 1.8x on STREAM and 1.5x peak I/O bandwidth, all against the previous generation.

Embedded customers get seven-year product availability, long-term BIOS and security support, and drop-in compatibility with the next generation in the same SP7 socket.

Production starts in November 2026. The 128-core SKU is available on November 15, with the rest expected in late December. ODM systems from Portwell, Lanner and IEI are expected to ship from January 2027.
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Nov 11th, 2026 03:07 CST change timezone

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