Wednesday, August 28th 2019

AMD to Cough Up $12.1 Million to Settle "Bulldozer" Core Count Class-Action Lawsuit

AMD reached a settlement in the Class Action Lawsuit filed against it, over alleged false-marketing of the core-counts of its eight-core FX-series processors based on the "Bulldozer" microarchitecture. Each member of the Class receives a one-time payout of USD $35 per chip, while the company takes a hit of $12.1 million. The lawsuit dates back to 2015, when Tony Dickey, representing himself in the U.S. District Court for the Northern District of California, accused AMD of false-marketing of its FX-series "Bulldozer" processor of having 8 CPU cores. Over the following four years, the case gained traction as a Class Action was built against AMD this January.

In the months that followed the January set-up of a 12-member Jury to examine the case, lawyers representing the Class and AMD argued over the underlying technology that makes "Bulldozer" a multi-core processor, and eventually discussed what a fair settlement would be for the Class. They eventually agreed on a number - $12.1 million, or roughly $35 per chip AMD sold, which they agreed was "fair," and yet significantly less than the "$60 million in premiums" consumers contended they paid for these processors. Sifting through these numbers, it's important to understand what the Class consists of. It consists of U.S. consumers who became interested to be part of the Class Action, and who bought an 8-core processor based on the "Bulldozer" microarchitecture. It excludes consumers of every other "Bulldozer" derivative (4-core, 6-core parts, APUs; and follow-ups to "Bulldozer" such as "Piledriver," "Excavator," etc.).
Image Credit: Taylor Alger Source: The Register
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288 Comments on AMD to Cough Up $12.1 Million to Settle "Bulldozer" Core Count Class-Action Lawsuit

#76
londiste
RichF, post: 4105796, member: 154826"
So, a wafer-scale processor could have 3,000 "quasi-cores" but it's a single-core chip if those "quasi-cores" share things other than cache?
If these quasi-cores share a frontend - yes, that would be a single-core chip.
Posted on Reply
#77
RichF
londiste, post: 4105798, member: 169790"
If these quasi-cores share a frontend - yes, that would be a single-core chip.
At which point were are in Neverland, where reality doesn't have anything to do with pedantism.
FordGT90Concept, post: 4105797, member: 60463"
Yes, that's pretty much what a GPU is.
Funny, then, how the industry doesn't refer to GPUs as single core. AMD, for example, has been counting cores for many years. Ooo... he can sue them over that, too!
Posted on Reply
#78
Vya Domus
londiste, post: 4105795, member: 169790"
L3 cache is not core.
Who gets to say this ? L1 and L2 didn't used to be core, they had their own sockets on the boards. FPUs didn't used to be core, they too had their own sockets on the board.

Do you see where this goes ? No matter where you go if you try and reduce this problems you always end up in the same place, the definition of a core is archaic and it is no longer relevant in modern times.

FordGT90Concept, post: 4105797, member: 60463"
That's a bandwidth issue, not a logic issue.
It has nothing to do with bandwidth, two entities try to write to the same addresses.

Can I write to it? Yes or not. It's a logic issue.
Posted on Reply
#79
ProPain
Stop all this .... :peace:

AMD ( Advanced Micro Devices, Inc ) was ruled = G.U.I.L.T.Y - that is 100% fact .... the Courts, however, decide on compensation claims.

And AMD is happy with this - and all AMD fanboys have to accept :banghead:!
Posted on Reply
#80
FordGT90Concept
"I go fast!1!11!1!"
Vya Domus, post: 4105800, member: 169281"
FPUs didn't used to be core, they too had their own sockets on the board ?
In the case of x87, it wasn't a core, it was a co-processor that could not function without an x86 master.
Posted on Reply
#81
londiste
Vya Domus, post: 4105800, member: 169281"
Who gets to say this ? L1 and L2 didn't used to be core, they had their own sockets on the boards. FPUs didn't used to be core, they too had their own sockets on the board ?
Core and CPU are defined by carrying out an instruction. In this thread, the context is x86, so x86 instructions. Core is a piece of logic that gets the instruction and outputs the result. L2 is in a bit of grey area as it does not really fit the classical core but today has become a necessary component to put right next to a core.

L3 fits in on a higher level, initially for communication between multiple CPUs - or today more commonly cores - as well as working with memory controller to make RAM less of a bottleneck. This is a multiprocessor system architecture - multiple processors and other logic units (IO Controller, RAM controller) on a shared bus (HyperTransport, Ring Bus, Infinity Fabric).

ProPain, post: 4105801, member: 152585"
AMD ( Advanced Micro Devices, Inc ) was ruled = G.U.I.L.T.Y - that is 100% fact .... the Courts, however, decide on compensation claims.
No it wasn't. It never got ruling in the court. AMD settled which means they decided that paying off the complaining parties was a more beneficial way of resolving this dispute.
Posted on Reply
#82
RichF
ProPain, post: 4105801, member: 152585"
Stop all this .... :peace:

AMD (Advanced Micro Devices, Inc ) was ruled = G.U.I.L.T.Y - that is 100% fact .... the Courts, however, decide on compensation claims.

And AMD is happy with this - and all AMD fanboy have to accept :banghead:!
The judge has to accept the settlement. Moreover, bad rulings are hardly rare. One of the most egregious trends in recent judicial incompetence is the fad for convicting physicians of murder for prescribing opioids to adults. This feeding frenzy of stupidity is also involving massive cash grabs by states and corrupt judges, as in Oklahoma.

People have been lamenting the judiciary's ineptitude when it comes to tech for a long time. Many can't even get the basic concept of physician and adult responsibility right — as if prescriptions don't have labels and as if adults have vanished from America, replaced by large kids. If judges can't understand basic concepts like adult personal responsibility one can't expect much when it comes to advanced tech that even experts apparently disagree on.
Posted on Reply
#83
ProPain
In the end - AMD is guilty!
Posted on Reply
#84
Vya Domus
londiste, post: 4105803, member: 169790"
Core and CPU are defined by carrying out an instruction. In this thread, the context is x86, so x86 instructions. Core is a piece of logic that gets the instruction and outputs the result. L2 is in a bit of grey area as it does not really fit the classical core but today has become a necessary component.
Where are these definitions ? Can you link books, papers anything ?

I have never in my life seen a core being labeled as the block that gets to execute instructions, that's usually simply called the ALU or execution unit. And the control portion gets to fetch and decode the instructions that are fed into the ALU.
Posted on Reply
#85
londiste
Vya Domus, post: 4105806, member: 169281"
Where are these definitions ? Can you link books, papers anything ?
Will try to search some books or papers.
Vya Domus, post: 4105806, member: 169281"
I have never in my life seen a core being labeled as the block that gets to execute instructions, that's usually simply called the ALU or execution unit. And the control portion gets to fetch and decode the instructions that are feed into the ALU.
At least when we are talking about x86 CPUs today - ALU or execution unit does not execute instructions. These execute (micro)operations. x86 instructions are often complex and are not executed directly or in a single cycle. This is where the decode part comes in - it breaks the instruction down to micro-operations that get sent to execution units.

For example, MOV between registers is a single micro-op that goes to one of the ALUs. MOV from register to memory is several cycles (4?) that involves both ALU and an AGU.
Posted on Reply
#86
Frick
Fishfaced Nincompoop
ProPain, post: 4105805, member: 152585"
In the end - AMD is guilty!
Technically, no.
Vya Domus, post: 4105806, member: 169281"
Where are these definitions ? Can you link books, papers anything ?

I have never in my life seen a core being labeled as the block that gets to execute instructions, that's usually simply called the ALU or execution unit. And the control portion gets to fetch and decode the instructions that are feed into the ALU.
That was wat I was going to ask. That is what it boils down to. If you define a "core" as a "complete single Pentium and upwards" then yeah sure. Is there even a definite definition of what a core is? Surely it has to be seen as contextual.


As for the architecture, it's not great but it has its upsides fo sho. A modern refined Bulldozer would be great for some specific applications.
Posted on Reply
#87
Zubasa
ProPain, post: 4105805, member: 152585"
In the end - AMD is guilty!
Common Law 101 = Any person / company is innocent unless proven guilty.
The court has to rule that they are guilty, not you.
Since that has not happened yet, they are legally not guilty.
Posted on Reply
#88
Vya Domus
londiste, post: 4105811, member: 169790"
At least when we are talking about x86 CPUs today
There's a good deal of fallacy in this. We talk about modern x86 CPUs today but we also get to say what's a core in all designs of all time ?
Posted on Reply
#89
londiste
Vya Domus, post: 4105815, member: 169281"
There's a good deal of fallacy in this. We talk about modern x86 CPUs today but we also get to say what's a core in all designs of all time ?
Core definition does not change.
Instructions may be (and are) different for other architectures (for example RISC or VLIW) and implementations can vary considerably.

Relevance of other instruction sets in context of Bulldozer - which is an x86 CPU - is questionable. I mean, academically, sure - we can say Integer Cluster is a CPU with whatever its micro-ops look like as an instruction set. But how would that be useful for an x86 CPU?
Posted on Reply
#90
Vya Domus
londiste, post: 4105816, member: 169790"
Relevance of other instruction sets in context of Bulldozer - which is an x86 CPU - is questionable. I mean, academically, sure - we can say Integer Cluster is a CPU with whatever its micro-ops look like as an instruction set. But how would that be useful for an x86 CPU?
What do you mean useful or an x86 CPU ? None of these things impact the "x86" portion of it, that would just be the instruction set. When you out a "not a core" stamp on something this is independent from the instruction set.

You want to talk about modern CPUs, why not talk about all CPUs ? That ought to be more relevant.

Don't selectively pick out this Integer Cluster out of all this and ask if that's useful or not, you need take the whole design and consider whether it's useful or not. And as far as I am concerned it is, it's a way to minimize resources while keeping most of the performance intact.

Academically, you can say this has been settled by the paper that describes this where the authors still consider this arrangement as being made up of cores, cores as in plural. Aren't these things peer reviewed ? Don't you think some one would have pointed out "Hey dumbass this is not a core" if that was the case ? We are talking about people far more knowledgeable on the subject that most of us on here.
Posted on Reply
#91
londiste
Vya Domus, post: 4105817, member: 169281"
What do you mean useful or an x86 CPU ? None of these things impact the "x86" portion of it, that would just be the instruction set. When you out a "not a core" stamp on something this is independent from the instruction set.
Core is defined via instructions.
Posted on Reply
#92
Vya Domus
londiste, post: 4105819, member: 169790"
Core is defined via instructions.
No it's not. I honestly don't even know how you come up with this, it's unbelievably out of place.
Posted on Reply
#93
Chloe Price
I was always like that FX was like "HT on steroids" instead of the core count advertised. Wasn't that wrong I guess.
Posted on Reply
#94
londiste
Vya Domus, post: 4105821, member: 169281"
No it's not. I honestly don't even know how you come up with this, it's unbelievably out of place.
How would you define a core?
Posted on Reply
#95
Vya Domus
londiste, post: 4105830, member: 169790"
How would you define a core?
By it's internals.

However, by instructions ? How would this work ?

Define me a dual core in terms of instructions, I am actually curios to see how this works.
Posted on Reply
#96
FordGT90Concept
"I go fast!1!11!1!"
Here you go:
https://en.wikipedia.org/wiki/X86_instruction_listings#Original_8086/8088_instructions

Look at those first ones...ASCII. Integer clusters don't even know what ASCII is because it has no reason to. A core (processor) can process overarching concepts like strings. Integer clusters and floating point clusters are tools the processing core uses to execute its instructions.

Like I said, AMD is trying to sell what was little more than a glorified calculator as a processor. In AMD's own technical documents, they stressed it's an "integer core" and not a processing core. That critical nuance was lost in AMD's marketing.


Edit: And this is why Bulldozer sucks: instructions have to be decoded twice: once to figure out ALU and FPU scheduling and again to actually execute it in their respective clusters. You can't get those extra cycles back.
Posted on Reply
#97
londiste
Vya Domus, post: 4105832, member: 169281"
However, by instructions ? How would this work ?
Define me a dual core in terms of instructions, I am actually curios to see how this works.
Actually, Wiki's CPU article starts with pretty much the right thing:
https://en.wikipedia.org/wiki/Central_processing_unit"
A central processing unit (CPU), also called a central processor or main processor, is the electronic circuitry within a computer that carries out the instructions of a computer program by performing the basic arithmetic, logic, controlling, and input/output (I/O) operations specified by the instructions.
Dual core and multicore are multiprocessor systems. Each core is a separate CPU in system connected via a bus.
Posted on Reply
#98
Vya Domus
londiste, post: 4105835, member: 169790"
Actually, Wiki's CPU article starts with pretty much the right thing:

Dual core and multicore are multiprocessor systems. Each core is a separate CPU in system connected via a bus.
:kookoo:

It doesn't start with everything, don't try to deflect this nonsense. I didn't ask if dual cores are multiprocessor systems.

How do you define a core by instructions ? What would be the instructions that would make something not a core ?
Posted on Reply
#99
londiste
Vya Domus, post: 4105842, member: 169281"
How do you define a core by instructions ?
Ok, let's take a step back.

Instruction is a specific term, not a generic one. There is a finite set of instructions you can feed to CPU that it is able to process called instruction set.
An example - MOV is a specific instruction in x86 instruction set that moves data from one location to another.
Extremely simple example - a calculator has instruction set of 4: addition, division, multiplication and division (lets assume no memory function or anything).

CPU is the piece that carries out these instructions.
From first example - x86 CPU needs to be able to do MOV. I will use the example above again - MOV with two registers as operand will use an ALU (part of execution stage and unit) and takes one cycle. MOV with register and a memory location as operand will use an ALU and AGU and will take a couple of cycles to complete.
Calculator example is simpler - these 4 instructions can be fed into execution stage pretty much directly, minor circuitry for fetch and no need for decode. Output can be fed directly to screen buffer.

When it comes to multicore CPUs, these are still defined based on a CPU and this is done via multiprocessor systems. Multiprocessor systems are simply what the name says - systems with multiple processors that are connected together. For multicore CPUs, the important part of these is mainly the homogeneous (in this context, same ISA) systems where multiple CPUs are in the same system connected together with a single bus. As time went by and technology evolved, the physical implementation has changed to put this onto a single die but both definition and principle are still the same. The only noteworthy addition to terminology is that a CPU in such situation is now called a core.

A note on that calculator example - the implementation of that instruction set is basically an ALU. Computer design course starts with building one pretty early on from gates and sometimes transistors, usually without the division though as that is a bit more complex to do. Although you physically need addition and multiplication - division is slight extra bit to addition circutry.
Posted on Reply
#100
Vya Domus
None of that has anything to do with your claim that cores can be defined as such.

The instructions set isn't tied to the hardware, instructions can't define hardware, they can't tell you what is a core or CPU and what isn't. Any turing complete computer can be made to carry out any kind of instruction no matter how simple or complex, people have figured this out a 100 years ago.

Point me to any instance in a any book or article that says something along the line of "this thing has a MOV instruction therefore it's a core", whenever this is brought up it's done so from a pure hardware perspective. As far as I am concerned you are literally making all of this up.
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