Thursday, June 25th 2026
Qualcomm HBC Gen 1 Achieves 133 TB/s Bandwidth by Stacking LPDDR Memory
Yesterday, Qualcomm announced its High Bandwidth Compute (HBC) product, a memory-compute solution hybrid designed to replace traditional High Bandwidth Memory (HBM) and offer greater performance, efficiency, and throughput. HBC utilizes LPDDR memory, stacking them across multiple layers in a 3D vertical space and interconnecting them with through-silicon vias (TSVs). This approach provides better energy efficiency than traditional HBM, which stacks regular DDR in vertical layers, as the low-power DDR (LPDDR) chips consume less power while delivering similar bandwidth and capacity. Qualcomm has successfully stacked multiple LPDDR layers on top of each other, with the base of the HBC being a compute die that performs near-memory computation and offloads some processing from the main processor.
This technique is similar to what HBM4 memory currently does, with the base die being a logic die to better integrate compute solutions underneath for packet tracing and data preparation for entering and exiting HBM. However, Qualcomm aims to achieve higher efficiency and more optimized data movement, with a 6x increase in bandwidth per watt compared to the current HBM specification, likely HBM4. HBC Gen 1 achieved 133 TB/s of bandwidth on the AI250 accelerator card, a 18x increase over the LPDDR5X currently used in the AI200 card from Qualcomm. The company also claims there is a viable roadmap for using HBC across many Qualcomm AI accelerators, with HBC Gen 1 shipping with the AI250 AI accelerator in mid-2027. The next-generation HBC Gen 2 is expected to yield further significant gains in bandwidth.
Currently, it is unclear where Qualcomm plans to source the LPDDR memory, which LPDDR memory version is used in HBC, and where the company plans to package this. Qualcomm is known for manufacturing its Snapdragon SoCs at TSMC, but the compute die could be manufactured by any memory maker partnering for the HBC launch. The most logical choice is Samsung Foundry, which manufactures both LPDDR in-house and offers custom logic manufacturing. However, this has yet to be confirmed by Qualcomm.
Source:
Qualcomm
This technique is similar to what HBM4 memory currently does, with the base die being a logic die to better integrate compute solutions underneath for packet tracing and data preparation for entering and exiting HBM. However, Qualcomm aims to achieve higher efficiency and more optimized data movement, with a 6x increase in bandwidth per watt compared to the current HBM specification, likely HBM4. HBC Gen 1 achieved 133 TB/s of bandwidth on the AI250 accelerator card, a 18x increase over the LPDDR5X currently used in the AI200 card from Qualcomm. The company also claims there is a viable roadmap for using HBC across many Qualcomm AI accelerators, with HBC Gen 1 shipping with the AI250 AI accelerator in mid-2027. The next-generation HBC Gen 2 is expected to yield further significant gains in bandwidth.
12 Comments on Qualcomm HBC Gen 1 Achieves 133 TB/s Bandwidth by Stacking LPDDR Memory
At 10.7 Gbit/s per pin, the fastest that's available now, this would require a 100,000-bit wide data bus... and that seems much closer to impossible than to possible.
The processor's internal data bus would have to be incredibly wide as well.
news.futunn.com/en/post/74875231/new-sandisk-patent-reveals-processor-directly-bonded-to-nand-flash?level=3&data_ticket=1782382185139265
In any case we'll have to wait for a proper whitepaper or device releases in 2027/2028. This is clearly PR information meant for investors.
If that were possible, it would further devastate the electronics market, since stacked memory in the HBM way uses many more chips and has terrible yields.
- The people buying those Qualcomm racks are technology experts
- The people buying those Qualcomm racks are easy to fool and manipulate
In other words, you don't like where the world is going/heading. The question is: can you change the trajectory and think of a better path that would appeal to people?Not exactly clear, typical marketing to get largest possible number on slide, but I believe this is bandwidth between memory and bottom layer (compute accelerator) connected with tons of these vias.
From what I found, when it needs to talk to outside, bandwidth is actually much lower than HBM