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Moore's Law - Is it Really Dead ?

"Moore's Law" is a term coined in 1965 by Gordon Moore, who presented a paper which predicts that semiconductor scaling will allow integrated circuits to feature twice as many transistors present per same area as opposed to a chip manufactured two years ago. That means we could get same performance at half the power than the previous chip, or double the performance at same power/price in only two years time. Today we'll investigate if Moore's Law stayed true to its cause over the years and how much longer can it keep going.

Intel Ships First 10nm Agilex FPGAs

Intel today announced that it has begun shipments of the first Intel Agilex field programmable gate arrays (FPGAs) to early access program customers. Participants in the early access program include Colorado Engineering Inc., Mantaro Networks, Microsoft and Silicom. These customers are using Agilex FPGAs to develop advanced solutions for networking, 5G and accelerated data analytics.

"The Intel Agilex FPGA product family leverages the breadth of Intel innovation and technology leadership, including architecture, packaging, process technology, developer tools and a fast path to power reduction with eASIC technology. These unmatched assets enable new levels of heterogeneous computing, system integration and processor connectivity and will be the first 10nm FPGA to provide cache-coherent and low latency connectivity to Intel Xeon processors with the upcoming Compute Express Link," said Dan McNamara, Intel senior vice president and general manager of the Networking and Custom Logic Group.

Intel Driving Data-Centric World with New 10nm Intel Agilex FPGA Family

Intel announced today a brand-new product family, the Intel Agilex FPGA. This new family of field programmable gate arrays (FPGA) will provide customized solutions to address the unique data-centric business challenges across embedded, network and data center markets. "The race to solve data-centric problems requires agile and flexible solutions that can move, store and process data efficiently. Intel Agilex FPGAs deliver customized connectivity and acceleration while delivering much needed improvements in performance and power for diverse workloads," said Dan McNamara, Intel senior vice president, Programmable Solutions Group.

Customers need solutions that can aggregate and process increasing amounts of data traffic to enable transformative applications in emerging, data-driven industries like edge computing, networking and cloud. Whether it's through edge analytics for low-latency processing, virtualized network functions to improve performance, or data center acceleration for greater efficiency, Intel Agilex FPGAs are built to deliver customized solutions for applications from the edge to the cloud. Advances in artificial intelligence (AI) analytics at the edge, network and the cloud are compelling hardware systems to cope with evolving standards, support varying AI workloads, and integrate multiple functions. Intel Agilex FPGAs provide the flexibility and agility required to meet these challenges and deliver gains in performance and power.

JEDEC Updates Groundbreaking High Bandwidth Memory (HBM) Standard

JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced the publication of an update to JESD235 High Bandwidth Memory (HBM) DRAM standard. HBM DRAM is used in Graphics, High Performance Computing, Server, Networking and Client applications where peak bandwidth, bandwidth per watt, and capacity per area are valued metrics to a solution's success in the market. The standard was developed and updated with support from leading GPU and CPU developers to extend the system bandwidth growth curve beyond levels supported by traditional discrete packaged memory. JESD235B is available for download from the JEDEC website.

JEDEC standard JESD235B for HBM leverages Wide I/O and TSV technologies to support densities up to 24 GB per device at speeds up to 307 GB/s. This bandwidth is delivered across a 1024-bit wide device interface that is divided into 8 independent channels on each DRAM stack. The standard can support 2-high, 4-high, 8-high, and 12-high TSV stacks of DRAM at full bandwidth to allow systems flexibility on capacity requirements from 1 GB - 24 GB per stack.

Samsung Unveils 256-Gigabyte 3DS DDR4 RDIMM, Other Datacenter Innovations

Samsung Electronics, a world leader in advanced semiconductor technology, today announced several groundbreaking additions to its comprehensive semiconductor ecosystem that encompass next-generation technologies in foundry as well as NAND flash, SSD (solid state drive) and DRAM. Together, these developments mark a giant step forward for Samsung's semiconductor business.

"Samsung's technology leadership and product breadth are unparalleled," said JS Choi, President, Samsung Semiconductor, Inc. "Bringing 7 nm EUV into production is an incredible achievement. Also, the announcements of SmartSSD and 256GB 3DS RDIMM represent performance and capacity breakthroughs that will continue to push compute boundaries. Together, these additions to Samsung's comprehensive technology ecosystem will power the next generation of datacenters, high-performance computing (HPC), enterprise, artificial intelligence (AI) and emerging applications."

Micron Announces Its Initial Launch Partner Status for NVIDIA RTX 20-Series GDDR6 Implementation

Memory subsystems are an important part of graphics workloads, and both AMD and NVIDIA have always been looking to cross the cutting-edge of tech in both GPU production and memory fabrication technologies. AMD has been hitching itself to the HBM bandwagon with much more fervor than NVIDIA, albeit with somewhat lukewarm results - at least from a consumer, gaming GPU perspective. NVIDIA has been more cautious: lock HBM's higher costs and lower availability to higher-margin products that can leverage the additional bandwidth, and leave GDDR to muscle its way through consumer products - a strategy that has likely helped in keeping BOM costs for its graphics cards relatively low.

As it stands, Micron was the only company with both the roadmap and production volume to be NVIDIA's partner in launching the RTX 20-series, with products above (and including) the GTX 2070 all carrying the new high-performance memory subsystem. Micron has already announced GDDR6 memory as a product back in 2017, with sampling by the beginning of 2018 and mass volume production by June - just enough time to spool up a nice inventory for new, shiny graphics cards to come out in September. Of course, this ramp-up and initial Micron leadership doesn't mean they will be the only suppliers for NVIDIA - however, it's safe to say they'll be the most relevant one for at least a good while.

AMD Announces Dual-Vega Radeon Pro V340 for High-Density Computing

AMD today at VMworld in Las Vegas announced their new, high-density computing, dual-GPU Radeon Pro V340 accelerator. This graphics card (or maybe accelerator) is based on the same Vega that makes AMD's consumer graphics card lineup, and crams its dual GPUs into a single card with a dual-slot design. 32 GB of second-generation Error Correcting Code (ECC) high-bandwidth memory (HBM) greases the wheels for the gargantuan amounts of data these accelerators are meant to crunch and power through, even as media processing requirements go through the roof.

Xilinx Unveils Their Revolutionary Adaptive Compute Acceleration Platform

Xilinx, Inc., the leader in adaptive and intelligent computing, today announced a new breakthrough product category called adaptive compute acceleration platform (ACAP) that goes far beyond the capabilities of an FPGA. An ACAP is a highly integrated multi-core heterogeneous compute platform that can be changed at the hardware level to adapt to the needs of a wide range of applications and workloads. An ACAP's adaptability, which can be done dynamically during operation, delivers levels of performance and performance per-watt that is unmatched by CPUs or GPUs.

An ACAP is ideally suited to accelerate a broad set of applications in the emerging era of big data and artificial intelligence. These include: video transcoding, database, data compression, search, AI inference, genomics, machine vision, computational storage and network acceleration. Software and hardware developers will be able to design ACAP-based products for end point, edge and cloud applications. The first ACAP product family, codenamed "Everest," will be developed in TSMC 7nm process technology and will tape out later this year.

NVIDIA to Unveil "Ampere" Based GeForce Product Next Month

NVIDIA prepares to make its annual tech expo, the 2018 Graphics Technology Conference (GTC) action-packed. The company already surprised us with its next-generation "Volta" architecture based TITAN V graphics card priced at 3 grand; and is working to cash in on the crypto-currency wave and ease pressure on consumer graphics card inventories by designing highly optimized mining accelerators under the new Turing brand. There's now talk that NVIDIA could pole-vault launch of the "Volta" architecture for the consumer-space; by unveiling a GeForce graphics card based on its succeeding architecture, "Ampere."

The oldest reports of NVIDIA unveiling "Ampere" date back to November 2017. At the time it was expected that NVIDIA will only share some PR blurbs on some of the key features it brings to the table, or at best, unveil a specialized (non-gaming) silicon, such as a Drive or machine-learning chip. An Expreview report points at the possibility of a GeForce product, one that you can buy in your friendly neighborhood PC store and play games with. The "Ampere" based GPU will still be based on the 12 nanometer silicon fabrication process at TSMC, and is unlikely to be a big halo chip with exotic HBM stacks. Why NVIDIA chose to leapfrog is uncertain. GTC gets underway late-March.

Intel Announces "Coffee Lake" + AMD "Vega" Multi-chip Modules

Rumors of the unthinkable silicon collaboration between Intel and AMD are true, as Intel announced its first multi-chip module (MCM), which combines a 14 nm Core "Coffee Lake-H" CPU die, with a specialized 14 nm GPU die by AMD, based on the "Vega" architecture. This GPU die has its own HBM2 memory stack over a 1024-bit wide memory bus. Unlike on the AMD "Vega 10" and "Fiji" MCMs, in which a silicon interposer is used to connect the GPU die to the memory stacks, Intel deployed the Embedded Multi-Die Interconnect Bridge (EMIB), a high-density substrate-level wiring. The CPU and GPU dies talk to each other over PCI-Express gen 3.0, wired through the package substrate.

This multi-chip module, with a tiny Z-height, significantly reduces the board footprint of the CPU + discrete graphics implementation, when compared to having separate CPU and GPU packages with the GPU having discrete GDDR memory chips, and enables a new breed of ultra portable notebooks that pack a solid graphics muscle. The MCM should enable devices as thin as 11 mm. The specifications of the CPU and dGPU dies remain under the wraps. The first devices with these MCMs will launch by Q1 2018.
A video presentation follows.

AMD "Navi" GPU by Q3-2018: Report

AMD is reportedly accelerating launch of its first GPU architecture built on the 7 nanometer process, codenamed "Navi." Graphics cards based on the first implementation of "Navi" could launch as early as by Q3-2018 (between July and September). Besides IPC increments with its core number-crunching machinery, "Navi" will introduce a slew of memory and GPU virtualization technologies.

AMD will take its multi-chip module (MCM) approach of building high-performance GPUs a step further, by placing multiple GPU dies with their HBM stacks on a single package. The company could leverage its InfinityFabric as a high-bandwidth interconnect between the GPU dies (dubbed "GPU module"), with an I/O controller die interfacing the MCM with the host machine. With multi-GPU on the decline for games, it remains to be seen how those multiple GPU modules are visible to the operating system. In the run up to "Navi," AMD could give its current "Vega" architecture a refresh on a refined 14 nm+ process, to increase clock speeds.

AMD's RX Vega to Feature 4 GB and 8 GB Memory

It looks like AMD is confident enough on its HBC (High-Bandwidth Cache) and HBCC (High-Bandwidth Cache Controller) technology, and other assorted improvements to overall Vega memory management, to consider 4 GB as enough memory for high-performance gaming and applications. On a Beijing tech summit, AMD announced that its RX Vega cards (the highest performers in their next generation product stack, which features rebrands of their RX 400 line series of cards to th new RX 500) will come in at 4 GB and 8 GB HBM 2 (512 GB/s) memory amounts. The HBCC looks to ensure that we don't see a repeat of AMD's Fury X video card, which featured first generation HBM (High-Bandwidth memory), at the time limited to 4 GB stacks. But lacking extensive memory management improvements meant that the Fury X sometimes struggled on memory-heavy workloads.

If the company's Vega architecture deep dive is anything to go by, they may be right: remember that AMD put out a graph showing how the memory allocation is almost twice as big as the actual amount of memory used - and its here, with smarter, improved memory management and allocation, that AMD is looking to make do with only 4 GB of video memory (which is still more than enough for most games, mind you). This could be a turn of the screw moment for all that "more is always better" philosophy.

AMD's Radeon Pro Duo Deeply Discounted on Expected Vega Onslaught

Inventory clearing is as much a part of business as breathing is part of life; as such, various retailers have apparently started to offer deep, deep discounts on AMD's past technology in the form of their Radeon Pro Duo - the once and still king of the hill in the red camp, where performance and technology is concerned.

But as the "out with the old, in with the new" adage still stands, retailers are now clearing inventory of their Radeon Pro Duo graphics cards, sometimes offering almost 50% off from the original launch price of $1499. Newegg, for example, has the card for $799 on both their North American and Asia Pacific online stores.

Third-Generation HBM Could Enable Graphics Cards with 64GB Memory

One of the first drafts of the HBM3 specification reveals that the standard could enable graphics cards with up to 64 GB of video memory. The HBM2 memory, which is yet to make its consumer graphics debut, caps out at 32 GB, and the first-generation HBM, which released with the AMD Radeon Fury series, at just 4 GB.

What's more, HBM3 doubles bandwidth over HBM2, pushing up to 512 GB/s per stack. A 4096-bit HBM3 equipped GPU could have up to 2 TB/s (yes, terabytes per second) of memory bandwidth at its disposal. SK Hynix, one of the key proponents of the HBM standard, even claims that HBM3 will be both more energy-efficient and cost-effective than existing memory standards, for the performance on offer. Some of the first HBM3 implementations could come from the HPC industry, with consumer implementations including game consoles, graphics cards, TVs, etc., following later.

AMD Provides Sneak Peek of Full Line of Radeon RX Series GPUs at E3

Today at Electronic Entertainment Expo (E3) AMD (NASDAQ: AMD) CEO Lisa Su delivered a pre-launch showcase of the full line of forthcoming Radeon RX Series graphics cards set to transform PC gaming this summer by delivering enthusiast class performance and features for gamers at mainstream price points. AMD previously showcased the Radeon RX 480 graphics card, designed for incredibly smooth AAA gaming at 1440p resolution and set to be the most affordable solution for premium VR experiences starting at just $199 SEP for the 4GB version. Joining the Radeon RX family are the newly announced Radeon RX 470 graphics card delivering refined, power-efficient HD gaming, and the Radeon RX 460, a cool and efficient solution for the ultimate e-sports gaming experience.

AMD's GPU Roadmap for 2016-18 Detailed

AMD finalized the GPU architecture roadmap running between 2016 and 2018. The company first detailed this at its Capsaicin Event in mid-March 2016. It sees the company's upcoming "Polaris" architecture, while making major architectural leaps over the current-generation, such as a 2.5-times performance/Watt uplift and driving the company's first 14 nanometer GPUs; being limited in its high-end graphics space presence. Polaris is rumored to drive graphics for Sony's upcoming 4K Ultra HD PlayStation, and as discrete GPUs, it will feature in only two chips - Polaris 10 "Ellesmere" and Polaris 11 "Baffin."

"Polaris" introduces several new features, such as HVEC (h.265) decode and encode hardware-acceleration, new display output standards such as DisplayPort 1.3 and HDMI 2.0; however, since neither Polaris 10 nor Polaris 11 are really "big" enthusiast chips that succeed the current "Fiji" silicon, will likely make do with current GDDR5/GDDR5X memory standards. That's not to say that Polaris 10 won't disrupt current performance-thru-enthusiast lineups, or even have the chops to take on NVIDIA's GP104. First-generation HBM limits the total memory amount to 4 GB over a 4096-bit path. Enthusiasts will have to wait until early-2017 for the introduction of the big-chip that succeeds "Fiji," which will not only leverage HBM2 to serve up vast amounts of super-fast memory; but also feature a slight architectural uplift. 2018 will see the introduction of its successor, codenamed "Navi," which features an even faster memory interface.

AMD FirePro S9300 x2 Server GPU Helps Create Largest Map of the Universe

AMD today announced that researchers at the Canadian Hydrogen Intensity Mapping Experiment (CHIME) will harness the AMD FirePro S9300 x2 Server GPU, the world's fastest single-precision GPU accelerator, to analyze extraordinary amounts of data to help create a new, very detailed 3D map of the largest volume of the Universe ever observed. Rather than using traditional dish-shaped telescopes, CHIME consists of four 100-metre-long cylindrical reflectors which cover an area larger than five professional hockey rinks and gathers signals for the critical computational analyses supplied by the AMD FirePro S9300 x2 GPU cluster.

The CHIME project was created to investigate the discovery that the expansion of the Universe is speeding up rather than slowing down. Using consumer technologies similar to those found in common radio receivers, the telescope collects radio waves that have travelled through space for up to 11 billion years and feeds them into a massive supercomputer powered by a series of AMD FirePro S9300 x2 GPUs. The intense number crunching required to map the Universe's expansion in this way was previously cost-prohibitive, but is now being enabled by AMD FirePro GPUs. The anticipated results will help create a highly-detailed map showing the intensity of the hydrogen radiation from billions of galaxies, which will help scientists understand the accelerating expansion of the Universe.

AMD Unveils the Radeon Pro Duo Graphics Card

AMD unveiled its latest flagship graphics card, the Radeon Pro Duo. The card is designed for "creators who game, and gamers who create," as the tagline goes. It is a dual-GPU graphics card based on a pair of 28 nm "Fiji" chips, the same ones which drive the R9 Fury X and the R9 Nano. AMD is positioning this card in the gray-area between consumer graphics cards, and FirePro workstation products, as a new "workstation-class" product. Perhaps this allows the company to get away with things such as three 8-pin PCIe power connectors.

The Radeon Pro Duo features two "Fiji" GPUs in their maximum core configuration - 4,096 stream processors, 256 TMUs, and 64 ROPs, each; with 4 GB of HBM memory, each. The card hence packs a total of 8 GB HBM memory, and 16 TFLOP/s total single-precision floating-point performance. The card features a liquid-cooling solution designed by Cooler Master, with a thick 120 mm x 120 mm radiator that's similar to the one that ships with the R9 Fury X. The card's display output configuration is similar to the R9 Fury X, too, with three DisplayPort 1.2a and one HDMI 1.4a connectors. AMD is going ahead and claiming the title of "World's Fastest Graphics Card." The Radeon R9 Pro Duo is expected to be priced at US $1,499.

SK Hynix to Ship 4GB HBM2 Stacks by Q3-2016

Korean DRAM and NAND flash giant SK Hynix will be ready to ship its 4 GB stacked second generation high-bandwidth memory (HBM2) chips from Q3, 2016. These packages will be made up of four 1 GB dies, with a bandwidth-per-pin of 1 Gbps, 1.6 Gbps, and 2 Gbps, working out to per-stack bandwidths of 128 GB/s, 204 GB/s, and 256 GB/s, respectively.

These chips will target applications such as graphics cards, network infrastructure, HPC, and servers. The company is also designing 8 GB stacks, made up of eight 1 GB dies. These stacks will be targeted at HPC and server applications. The company is also offering cost-effective 2 GB, 2-die stacks, for graphics cards. The cost-effective 2 GB, 2-die stacks could prove particularly important for the standard's competition against GDDR5X, particularly in mid-range and performance-segment graphics cards.

JEDEC Updates Groundbreaking High Bandwidth Memory (HBM) Standard

JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced the publication of an update to JESD235 High Bandwidth Memory (HBM) DRAM standard. HBM DRAM is used in Graphics, High Performance Computing, Server, Networking and Client applications where peak bandwidth, bandwidth per watt, and capacity per area are valued metrics to a solution's success in the market. The standard was developed and updated with support from leading GPU and CPU developers to extend the system bandwidth growth curve beyond levels supported by traditional discrete packaged memory. JESD235A is available for free download from the JEDEC website.

JESD235A leverages Wide I/O and TSV technologies to support up to 8 GB per device at speeds up to 256 GB/s. This bandwidth is delivered across a 1024-bit wide device interface that is divided into 8 independent channels on each DRAM stack. The standard supports 2-high, 4-high and 8-high TSV stacks of DRAM at full bandwidth to allow systems flexibility on capacity requirements from 1 GB - 8 GB per stack.

Sapphire Unveils TriXX with "Fiji" Voltage Control and HBM Overclocking

Sapphire announced its latest version of the TriXX overclocking utility, which it bundles with its graphics cards. Version 5.2.1 is one of the first pieces of software to support voltage control on AMD "Fiji" GPU graphics cards (R9 Fury, R9 Fury X, and R9 Nano), and HBM overclocking. The utility comes with a new "dashboard" themed user interface that gives you an analog readout of your card's main sensors - clocks, voltage, and temperatures; and a simpler layout. In addition, it also supports voltage control on other Radeon R9 300 series GPUs.
DOWNLOAD: Sapphire TriXX 5.2.1

AMD "Fiji" GPU Die-shot Revealed by Chipworks

VLSI technical publication Chipworks posted the first clear die-shot of AMD's "Fiji" silicon, revealing intricate details of the most technically advanced GPU. What makes Fiji the most advanced graphics chip is its silicon interposer and stacked HBM chips making up a multi-chip module. It's the die in the center of all that, which went under Chipworks' microscope.

The die-shot reveals a component layout that's more or less an upscale of "Tonga." Some of the components, such as the front-end appear to be entirely identical to "Tahiti" or "Tonga." The shot reveals the 64 GCN compute units arranged in four rows, on either side of the central portion with the dispatch and primitive setup pipelines. The pad-area of the on-die memory controllers appear to be less than the large memory I/O pads that made up the 384-bit interface of "Tahiti." The first picture below is the die-shot of "Fiji," followed by a color-coded die-shot of "Tahiti."

AMD Radeon R9 Nano Core Configuration Detailed

AMD's upcoming mini-ITX friendly graphics card, the Radeon R9 Nano, which boasts of a typical board power of just 175W, is not a heavily stripped-down R9 Fury X, as was expected. The card will feature the full complement of GCN compute units physically present on the "Fiji" silicon, and in terms of specifications, is better loaded than even the R9 Fury. Specifications sheet of the R9 Nano leaked to the web, revealing that the card will feature all 4,096 stream processors physically present on the chip, along with 256 TMUs, and 64 ROPs. It will feature 4 GB of memory across the chip's 4096-bit HBM interface.

In terms of clock speeds, the R9 Nano isn't too far behind the R9 Fury X on paper - its core is clocked up to 1000 MHz, with its memory ticking at 500 MHz (512 GB/s). So how does it get down to 175W typical board power, from the 275W of the R9 Fury X? It's theorized that AMD could be using an aggressive power/temperature based clock-speed throttle. The resulting performance is 5-10% higher than the Radeon R9 290X, while never breaching a power target. Korean tech blog DGLee posted pictures of an R9 Nano taken apart. Its PCB is smaller than even that of the R9 Fury X, and makes do with a slimmer 4+2 phase VRM, than the 6+2 phase VRM found on the R9 Fury X.

AMD Showcases Graphics, Energy Efficient Computing and Die-Stacking Innovation

Top technologists from AMD are detailing the engineering accomplishments behind the performance and energy efficiency of the new high-performance Accelerated Processing Unit (APU), codenamed "Carrizo," and the new AMD Radeon R9 Fury family of GPUs, codenamed "Fiji," at the prestigious annual Hot Chips symposium starting today. The presentations will focus on new details of the high-definition video and graphics processing engines on the 6th Generation AMD A-Series APU ("Carrizo"), and the eight year journey leading to die-stacking technology and all-new memory architecture included on the latest top-of-the-line AMD Radeon Fury Series GPUs ("Fiji") for 4K gaming and VR. Using a true System-on-Chip (SoC) design, 6th Generation AMD A-Series processors are designed to reduce the power consumed by the x86 cores alone by 40 percent, while providing substantial gains in CPU, graphics, and multimedia performance versus the prior generation APU. The new AMD Radeon R9 Fury X GPU achieves up to 1.5x the performance-per-watt of the previous high-end GPU from AMD.

"With our new generation of APU and GPU technology, our engineering teams left no stone unturned for performance and energy efficiency," said Mark Papermaster, chief technology officer at AMD. "Using innovative design for our APUs, we've vastly increased the number of transistors on-chip to increase functionality and performance, implemented advanced power management, and completed the hardware implementation of Heterogeneous System Architecture. For our latest GPUs, AMD is the first to introduce breakthrough technology in the form of die-stacking and High-Bandwidth Memory. The results are great products with very large generational performance-per-watt gains."

EK Radeon R9 Fury X Water Blocks Now Available

EK Water Blocks, Ljubljana based premium computer liquid cooling gear manufacturer, is excited to launch the true single-slot liquid cooling solution for AMD Radeon reference design R9 FURY X graphics card. EK-FC R9 Fury X directly cools the GPU, HBM as well as VRM (voltage regulation module) as water flows directly over these critical areas, thus allowing the graphics card and it's VRM to remain stable under high overclocks.

EK-FC R9 Fury X water block features EK unique central inlet split-flow cooling engine design for best possible cooling performance. Such system also works flawlessly with the reversed water flow without adversely affecting the cooling performance. Moreover, such design offers great hydraulic performance, allowing this product to be used in liquid cooling systems using weaker water pumps. Unlike the original AIO cooling solution that comes with AMD Radeon R9 FURY X and takes up two slots, EK-FC R9 Fury X water block will transform the FURY X into a single-slot graphics card.
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