NVIDIA today provided more details about its latest custom Armv9.2 "Vera" CPU, which the company describes as a pinnacle of its CPU engineering. Designed to coexist within NVL rackscale systems or operate independently, NVIDIA has seen significant interest from its customers in deploying the "Vera" CPU across enterprises. The company optimized its design for data analysis, high-performance single-threaded tasks, agentic AI, and large-scale software operations, covering a wide range of use cases. The entire "Olympus" CPU core is divided into four major areas: front end, mid-core, execution engine, and cache subsystems. In the front end, NVIDIA has developed a branch predictor that works actively with the instruction fetching unit to keep the core supplied with useful instructions. Tasks such as agent runtimes, compilers, and large data processing workloads often involve control-flow changes, which can leave execution units in the CPU idle. The "Olympus" core uses a 10-wide decode engine to ensure a continuous flow of instructions to execution units, keeping them fully utilized. To prepare the data path for execution, NVIDIA created a neural branch predictor that reduces the execution of incorrect paths, supporting up to two taken branches per cycle. This is crucial for control-flow changes when software execution on large data processing suddenly shifts.Next is the mid-core, or the rename section inside "Olympus." This part of the CPU core is designed to uncover independent work while other parts of the CPU are waiting. This means the re-order buffer is constantly loading instructions for execution, allowing out-of-order execution to reach greater depth. Rename and allocation maps decode instructions to physical resources, and together these features exploit instruction parallelism to maintain productive execution, especially in software workflows that change suddenly.

For executing these prepared instructions, NVIDIA's execution engine takes over. As instructions are broken down into microoperations, each microoperation is assigned to its respective scalar or vector processing engine. The "Olympus" execution engine has a dynamic schedule that distributes these scalar, vector, floating-point, cryptographic, and load/store resource microoperations with low latency, enabling a much higher number of instructions processed per second. NVIDIA has not revealed much about this part, as it is likely where most of the innovation occurs within the new core design.

To complete the system, NVIDIA's cache subsystem is designed to quickly retrieve data from outside the CPU. Agentic AI workloads are demanding because they require data that doesn't fit within the CPU cache, necessitating high throughput to retrieve sparse data, databases, runtime objects, retrieval indexes, and many other data structures. The "Olympus" core features a deep cache hierarchy, multiple prefetch engines for faster data retrieval, and dedicated prefetchers for graph data.

One of the main differences between traditional x86 CPUs with simultaneous multithreading is that these designs create two hardware threads that share a single core. In modern environments, this can lead to a "noisy neighbor" effect where two threads compete for the same resources, causing stalls. NVIDIA addresses this issue with simultaneous multithreading that partitions resources before assigning them to each thread, as the width of the "Olympus" core allows for instantaneous resource partitioning, ensuring every task is effectively distributed.

Connecting the entire system is NVIDIA's Scalable Coherency Fabric, which offers 3.4 TB/s of fabric bandwidth and integrates a 164 MB unified L3 cache across the CPU die. External connections include SOCAMM2 LPDDR5X memory, running at 1.2 TB/s of aggregate bandwidth, with NVIDIA shipping up to 1.5 TB of LPDDR5X memory per CPU. The company showed some preliminary performance comparison with AMD EPYC "Turin" 9755 CPU on per-core performance, claiming up to 1.8x performance boost in select workloads.