TSMC is reportedly developing an advanced packaging technology to rival Intel's Embedded Multi-die Interconnect Bridge (EMIB), which the company internally refers to as EMIB-like. According to sources close to The Information, TSMC's Chip-on-Wafer-on-Substrate (CoWoS) packaging might lose some customers to Intel's EMIB. As a result, TSMC has begun developing its EMIB-like technology. This development will reportedly be supported by Taiwan's Kinsus Interconnect Technology, which will assist TSMC in developing, scaling, and manufacturing the CoWoS alternative without issues. TSMC currently offers three versions of CoWoS: CoWoS-S, CoWoS-L, and CoWoS-R.

CoWoS-S is the first generation of CoWoS, utilizing a full monolithic silicon interposer with TSVs for maximum routing density and performance. Then, there is CoWoS-L that takes a hybrid approach, replacing the full silicon sheet with a more affordable organic base and embedding small localized silicon bridges (LSI) only where high-speed die-to-die communication occurs. This allows for large layouts to bypass reticle limits through bridge stitching. CoWoS-R is the third option that completely replaces silicon with an organic copper/polymer RDL interposer. It experiences a slight reduction in signal attenuation and routing density, but its mechanical flexibility makes it highly scalable and cost-effective for large-die chips.Intel's advanced packaging portfolio allows designers to use 2D, 2.5D, and 3D building blocks to optimize cost, power, and bandwidth at the system level. EMIB is a substrate-embedded silicon bridge that provides localized, high-density die-to-die routing without the cost and area penalty of a full-size silicon interposer. For example, small silicon EMIB bridges—available in variants like EMIB-M with embedded MIM capacitors and EMIB-T with TSVs—offer low-cost, high-density shoreline connections ideal for logic-to-logic and logic-to-HBM interfaces.