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Tianshu Zhixin Big Island GPU is a 37 TeraFLOP FP32 Computing Monster

Tianshu Zhixin, a Chinese startup company dedicated to designing advanced processors for accelerating various kinds of tasks, has officially entered the production of its latest GPGPU design. Called "Big Island" GPU, it is the company's entry into the GPU market, currently dominated by AMD, NVIDIA, and soon Intel. So what is so special about Tianshu Zhixin's Big Island GPU, making it so important? Firstly, it represents China's attempt of independence from the outside processor suppliers, ensuring maximum security at all times. Secondly, it is an interesting feat to enter a market that is controlled by big players and attempt to grab a piece of that cake. To be successful, the GPU needs to represent a great design.

And great it is, at least on paper. The specifications list that Big Island is currently being manufactured on TSMC's 7 nm node using CoWoS packaging technology, enabling the die to feature over 24 billion transistors. When it comes to performance, the company claims that the GPU is capable of crunching 37 TeraFLOPs of single-precision FP32 data. At FP16/BF16 half-precision, the chip is capable of outputting 147 TeraFLOPs. When it comes to integer performance, it can achieve 317, 147, and 295 TOPS in INT32, INT16, and IN8 respectively. There is no data on double-precision floating-point numbers, so the chip is optimized for single-precision workloads. There is also 32 GB of HBM2 memory present, and it has 1.2 TB of bandwidth. If we compare the chip to the competing offers like NVIDIA A100 or AMD MI100, the new Big Island GPU outperforms both at single-precision FP32 compute tasks, for which it is designed.
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Pictures of possible solutions follow.

Chinese Tianshu Zhixin Announces Big Island GPGPU on 7 nm, 24 billion Transistors

Chinese company Shanghai Tianshu Zhixin Semiconductor Co., Ltd., commonly known (at least in Asia) as Tianshu Zhixin, has announced the availability of their special-purpose GPGPU, affectionately referred to as Big Island (BI). The BI chip is the first fully domestic-designed solution for the market it caters to, and features close to the latest in semiconductor manufacturing, being built on a 7 nm process featuring 2.5D CoWoS (chip-on-wafer-on-substrate) packaging. The chip is built towards AI and HPC applications foremost, with applications in other industries such as education, medicine, and security. The manufacturing and packaging processes seem eerily similar to those available from Taiwanese TSMC.

Tianshu Zhixin started work on the BI chip as early as 2018, and has announced that the chip features support for most AI and HPC data processing formats, including FP32, FP16, BF16, INT32, INT16, and INT8 (this list is not exhaustive). The company says the chip offers twice the performance of existing mainstream products on the market, and emphasizes its price/performance ratio. The huge chip (it packs as many as 24 billion transistors) is being teased by the company as offering as much as 147 TFLOPs in FP126 workloads, compared to 77.97 TFLOPs in the NVIDIA A100 (54 billion transistors) and 184.6 TFLOPS from the AMD Radeon Instinct MI100 (estimated at 50 billion transistors).

TSMC to Enter Mass Production of 6th Generation CoWoS Packaging in 2023, up to 12 HBM Stacks

TSMC, the world's leading semiconductor manufacturing company, is rumored to start production of its 6th generation Chip-on-Wafer-on-Substrate (CoWoS) packaging technology. As the silicon scaling is getting ever so challenging, the manufacturers have to come up with a way to get as much performance as possible. That is where TSMC's CoWoS and other chiplet technologies come. They allow designers to integrate many integrated circuits on a single package, making for a cheaper overall product compared to if the product used one big die. So what is so special about 6th generation CoWoS technology from TSMC, you might wonder. The new generation is said to enable a massive 12 stacks of HBM memory on a package. You are reading that right. Imagine if each stack would be an HBM2E variant with 16 GB capacity that would be 192 GB of memory on the package present. Of course, that would be a very expensive chip to manufacture, however, it is just a showcase of what the technology could achieve.

Update 16:44 UTC—The English DigiTimes report indicates that this technology is expected to see mass production in 2023.

TSMC Begins Construction of 2 nm Manufacturing Facility

TSMC, the leading semiconductor foundry in the world, has reportedly begun construction of its 2 nm manufacturing facility. According to a DigiTimes report, translated by @chiakokhua on Twitter, besides the construction of 2 nm R&D center, TSMC has also started the construction of the manufacturing facility for that node, so it will be ready in time. Please do note that the node name doesn't represent the size of the transistor, so it will not actually be 2 nm wide. The new facilities will be located near TSMC's headquarters in Hsinchu Science Park, Taiwan. The report also confirms the first details about the node, specifically that it will use Gate-All-Around (GAA) technology. And there is also another interesting piece of information regarding even smaller node, the planning for 1 nm node has begun according to the source.

Besides advanced nodes, TSMC also laid out clear plans to accelerate the push of advanced packaging technology. That includes SoIC, InFO, CoWoS, and WoW. All of these technologies are classified as "3D Fabric" by the company, even though some are 2.5D. These technologies will be mass-produced at "ZhuNan" and "NanKe" facilities starting in the second half of 2021, and are expected to significantly contribute to the company's profits. It is also reported that the competing foundry, Samsung, has a 3D packaging technology of its own called X-cube, however, it is attracting customers a lot slower than TSMC due to the high costs of the new technology.

Rambus Advances HBM2E Performance to 4.0 Gbps for AI/ML Training Applications

Rambus Inc. (NASDAQ: RMBS), a premier silicon IP and chip provider making data faster and safer, today announced it has achieved a record 4 Gbps performance with the Rambus HBM2E memory interface solution consisting of a fully-integrated PHY and controller. Paired with the industry's fastest HBM2E DRAM from SK hynix operating at 3.6 Gbps, the solution can deliver 460 GB/s of bandwidth from a single HBM2E device. This performance meets the terabyte-scale bandwidth needs of accelerators targeting the most demanding AI/ML training and high-performance computing (HPC) applications.

"With this achievement by Rambus, designers of AI and HPC systems can now implement systems using the world's fastest HBM2E DRAM running at 3.6 Gbps from SK hynix," said Uksong Kang, vice president of product planning at SK hynix. "In July, we announced full-scale mass-production of HBM2E for state-of-the-art computing applications demanding the highest bandwidth available."

TSMC Details 3nm N3, 5nm N5, and 3DFabric Technology

TSMC on Monday kicked off a virtual tech symposium, where it announced its new 12 nm N12e node for IoT edge devices, announced the new 3DFabric Technology, and detailed progress on its upcoming 5 nm N5 and 3 nm N3 silicon fabrication nodes. The company maintains that the N5 (5 nm) node offers the benefits of a full node uplift over its current-gen N7 (7 nm), which recently clocked over 1 billion chips shipped. The N5 node incorporates EUV lithography more extensively than N6/N7+, and in comparison to N7 offers 30% better power at the same performance, 15% more performance at the same power, and an 80% increase in logic density. The company has commenced high-volume manufacturing on this node.

2021 will see the introduction and ramp-up of the N5P node, an enhancement of the 5 nm N5 node, offering a 10% improvement in power at the same performance, or 5% increase in performance at the same power. A nodelet of the N5 family of nodes, called N4, could see risk production in Q4 2021. The N4 node is advertised as "4 nm," although the company didn't get into its iso-power/iso-performance specifics over the N5 node. The next major node for TSMC will be the 3 nm N3 node, with massive 25%-30% improvement in power at the same performance, or 10%-15% improvement in performance at same power, compared to N5. It also offers a 70% logic density gain over N5. 3DFabric technology is a new umbrella term for TSMC's CoWoS (chip on wafer on substrate), CoW (chip on wafer), and WoW (wafer on wafer) 3-D packaging innovations, with which it plans to offer packaging innovations that compete with Intel's various new 3D chip packaging technologies on the anvil.

TSMC Sees Higher Demand for CoWoS Packaging

TSMC, Taiwan's flagship manufacturer of silicon, has seen a substantial increase in demand for Chip-on-Wafer-on-Substrate (CoWoS) packaging technology, according to the report from DigiTimes. CoWoS is a multi-chip packaging technology that gives an option to build silicon like LEGO, allowing for dies to be placed side by side on interposer that is providing high interconnect density and performance. You can see more about CoWoS in detail here. Some of the examples of CoWoS are NVIDIA's P100 and V100 dies that integrate logic (computing elements), and memory (in the form of HBM) on a single die.

Recently, TSMC updated its CoWoS technology, where this new second-generation parts could scale far larger than the first-generation implementation - up to 1700 squared millimeters of die space, allowing for some very creative solutions to be implemented. This may be the reason that the demand in Q2 has risen so substantially and that TSMC's production lines are now running at full capacity, trying to meet the demand for this packaging technology.
TSMC CoWoS NVIDIA V100
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