Tuesday, October 13th 2026
Intel Refers to its 3D V-Cache Analog as "BFC"
Intel is introducing its analog to AMD's 3D V-Cache technology with its upcoming Core Ultra Series 4 "Nova Lake" desktop processors. We've known for over a year now, that the company is introducing SKUs with enlarged last-level caches. Technical docs leaks have until now referred to this technology as "bLLC," which simply meant "big last-level cache." We weren't sure if bLLC would be used as a marketing name for the tech, and it turns out, we're right. Apparently, Intel is going with "BFC" as the brand-extension for processor models featuring bLLC.
As we head closer to product launches of these next-generation chips, processor model numbering for these chips have begun to surface. The series will retain the new Core Ultra naming scheme from the current Core Ultra Series 2 "Arrow Lake" generation, but augment this with 4-digit model numbering that somewhat resembles the 4th Gen Core "Haswell" series. The "K" and "KF" brand extensions refer to the chips featuring an upwards unlocked base frequency multiplier; whereas "BFC" refers to the presence of bLLC.It's anyone's guess what "BFC" abbreviates; Intel probably has some clever marketing name for that acronym, such as "big fusion cache," and of course gamers would know what "F" word substitute to use here.
The idea behind bLLC is the same as AMD had for 3D V-Cache. AMD discovered that enlarging the L3 cache of the processor can significantly improve gaming performance of the processor as it places more of the fast-moving game data, such as textures within 1/6th the latency of DRAM. While AMD stacks a slab of L3 cache memory on top of its CCD, over the central region with the on-die L3 cache to achieve a contiguously addressable cache block; Intel may use a different approach, such as having a cache tile sitting beside the Compute tile, with the ringbus of the compute-complex being extended to it, or short-terminating in the absence of it.
Sources:
LC Tech Leaks, VideoCardz
As we head closer to product launches of these next-generation chips, processor model numbering for these chips have begun to surface. The series will retain the new Core Ultra naming scheme from the current Core Ultra Series 2 "Arrow Lake" generation, but augment this with 4-digit model numbering that somewhat resembles the 4th Gen Core "Haswell" series. The "K" and "KF" brand extensions refer to the chips featuring an upwards unlocked base frequency multiplier; whereas "BFC" refers to the presence of bLLC.It's anyone's guess what "BFC" abbreviates; Intel probably has some clever marketing name for that acronym, such as "big fusion cache," and of course gamers would know what "F" word substitute to use here.
The idea behind bLLC is the same as AMD had for 3D V-Cache. AMD discovered that enlarging the L3 cache of the processor can significantly improve gaming performance of the processor as it places more of the fast-moving game data, such as textures within 1/6th the latency of DRAM. While AMD stacks a slab of L3 cache memory on top of its CCD, over the central region with the on-die L3 cache to achieve a contiguously addressable cache block; Intel may use a different approach, such as having a cache tile sitting beside the Compute tile, with the ringbus of the compute-complex being extended to it, or short-terminating in the absence of it.


62 Comments on Intel Refers to its 3D V-Cache Analog as "BFC"
BFG - Big Frendly Giant.
BFG - Big F'n Gun
....
BFC - Big F'n Cache
All this money for R&D and that's the best they could have come up with?
So, Intel's critique of AMD's 3D V-cache was just envy? (All respect to Robert Hallock and his humble approach in the interview with PCHG)
Big Beautiful Cache
John Rambo wouldn't approve.
I'm not even mad. I'm surprised.
I'm waiting for the finished product. Does it have 3 or 5 different cores with 10 different cpu instruction and no common ground? does it have already established cpu instructions? Or does it have only cpu instructions from year 2000 for legacy computing?
I am curious about 2 cpu cores + 10 trash cores + 30 electrical waste cores with hardly any cpu instructions + 1gib of total cache. I will wait until the product can be purchased. Than i will look into it. Anything else is just speculations without any facts.
-- More cache is better was a known fact since at least year 2000 for myself. I would not state amd discovered it. Intel 5th series also showed that, now we are around intel 17 or 18th gen - i do not care for intel renaming tactics etc.
On the Architecture/Series part all of them are labeled as "Nova Lake S 28C", with some having the BLLC and others don't. However, on the description column we can see that only a single model actually has 28C in total (8P+16E+4L), which also has the BLLC.
So, that 28C seems to be the description of the base die, with only that 4970k getting the full die plus the BLLC, whereas all others are just lower binnings, right?
If the above is correct, it also seems that only the models which have the 4 LP cores will be the ones getting the BLLC. Is the tile for the BLLC also the same for those cores? I thought those LP cores would be on some kind of SoC tile. If that's also the case, it'd then explain why there are no variants with the same core config without the BLLC.