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Intel DG2 Discrete Xe Graphics Block Diagram Surfaces

New details have leaked on Intel's upcoming DG2 graphics accelerator, which could help shed some light on what exactly can be expected from Intel's foray into the discrete graphics department. For one, a product listing shows an Intel DG2 graphic accelerator being paired with 8 GB of GDDR6 memory and a Tiger Lake-H CPU (45 W version with 8 cores, which should carry only 32 EUs in integrated graphics hardware). This 8 GB of GDDR6 detail is interesting, as it points towards a 256-bit memory bus - one that is expected to be paired with the 512 EU version of Intel's DG2 (remember that a 384 EU version is also expected, but that one carries only 6 GB of GDDR6, which most likely means a 192-bit bus.

Videocardz says they have received an image for the block diagram on Intel's DG2, pointing towards a 189 mm² die area for the 384 EU version. Looking at component density, it seems that this particular diagram may refer to an MXM design, commonly employed as a discrete notebook solution. 6 total GDDR6 chips are seen in the diagram, thus pointing towards a memory density of 6 GB and the aforementioned 192-bit bus. Other specs that have turned up in the meantime point towards a USB-C interface being available for the DG2, which could either point towards a Thunderbolt 4-supporting design, or something like Virtual Link.
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