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NVIDIA to Acquire Arm for $40 Billion, Creating World's Premier Computing Company for the Age of AI

NVIDIA and SoftBank Group Corp. (SBG) today announced a definitive agreement under which NVIDIA will acquire Arm Limited from SBG and the SoftBank Vision Fund (together, "SoftBank") in a transaction valued at $40 billion. The transaction is expected to be immediately accretive to NVIDIA's non-GAAP gross margin and non-GAAP earnings per share.

The combination brings together NVIDIA's leading AI computing platform with Arm's vast ecosystem to create the premier computing company for the age of artificial intelligence, accelerating innovation while expanding into large, high-growth markets. SoftBank will remain committed to Arm's long-term success through its ownership stake in NVIDIA, expected to be under 10 percent.

Rambus Advances HBM2E Performance to 4.0 Gbps for AI/ML Training Applications

Rambus Inc. (NASDAQ: RMBS), a premier silicon IP and chip provider making data faster and safer, today announced it has achieved a record 4 Gbps performance with the Rambus HBM2E memory interface solution consisting of a fully-integrated PHY and controller. Paired with the industry's fastest HBM2E DRAM from SK hynix operating at 3.6 Gbps, the solution can deliver 460 GB/s of bandwidth from a single HBM2E device. This performance meets the terabyte-scale bandwidth needs of accelerators targeting the most demanding AI/ML training and high-performance computing (HPC) applications.

"With this achievement by Rambus, designers of AI and HPC systems can now implement systems using the world's fastest HBM2E DRAM running at 3.6 Gbps from SK hynix," said Uksong Kang, vice president of product planning at SK hynix. "In July, we announced full-scale mass-production of HBM2E for state-of-the-art computing applications demanding the highest bandwidth available."

Western Digital Sets a New Standard in Data Protection with Ground-Breaking ArmorLock Security Platform

Underscoring its mission to enable the world to solve its biggest data challenges by building a data infrastructure with next-gen security, Western Digital (NASDAQ: WDC) today introduced the ArmorLock Security Platform. A data encryption platform that rethinks how data security should be done, the ArmorLock Security Platform was created to help with the diverse security demands of data-centric and content-critical storage use cases in industries as varied as finance, government, healthcare, IT enterprise, legal, and media and entertainment. As data security concerns continue to rise in visibility, Western Digital plans to apply the platform across a range of storage solutions.

The first product to leverage this advanced technology, the new G-Technology ArmorLock encrypted NVMe SSD, is designed to deliver an easy-to-use, high-performance, high-grade security storage solution for creators in the media and entertainment industry. Facing the threat of hijacked media files and leaked films, studios, agencies, and especially investors are demanding a better way to protect critical content. While much of the industry's focus has been on cloud security, data often remains vulnerable on the portable storage devices holding critical commercial content.

Arm and DARPA Sign Partnership Agreement to Accelerate Technological Innovation

Arm today announced a three-year partnership agreement with the U.S. Defense Advanced Research Projects Agency (DARPA), establishing an access framework to all commercially available Arm technology. With DARPA's Electronics Resurgence Initiative gaining momentum, the new agreement will enable the research community that supports DARPA's programs to quickly and easily take advantage of Arm's leading IP, tools and support, accelerating innovation in a variety of fields.

"The span of DARPA research activity opens up a huge range of opportunities for future technological innovation," said Rene Haas, president, IP Products Group, Arm. "Our expanded DARPA partnership will provide them with access to the broadest range of Arm technology to develop compute solutions supported by the world's largest ecosystem of tools, services and software."

Samsung Aims to Become Number One Android AP Vendor by Joining Forces with AMD and Arm

Samsung Electronics has reportedly laid out a plan to become the number one Android application processor (AP) vendor in the industry with its plan to join forces with AMD and Arm. The report of Business Korea indicates that Samsung wants to use both company's knowledge and IP to produce the best possible silicon. In early November of last year, Samsung has decided to shut down its division responsible for making custom CPU designs, and to start licensing IP from Arm. Also last year, Samsung has announced a strategic partnership with AMD to use its RDNA graphics processors in smartphones.

So Samsung plans to license IPs from both companies and just put them in SoC that will be up to the task to deliver the best performance, as the company predicts. The CPU is reportedly going to be based on Arm's Cortex-X custom design that should deliver high-performance Samsung wants. In the past, the company had some problems with the heat-management of its CPUs as they were designed a bit inefficiently. To cover everything, Samsung also plans to increase the number of employees working on a neural processing unit (NPU) and make a good performing NPUs as well, to combine with the rest of IPs.

Intel Rocket Lake CPUs Will Bring up to 10% IPC Improvement and 5 GHz Clocks

Intel is struggling with its node development and it looks like next-generation consumer systems are going to be stuck on 14 nm for a bit more. Preparing for that, Intel will finally break free from Skylake-based architectures and launch something new. The replacement for the current Comet Lake generation is set to be called Rocket Lake and today we have obtained some more information about it. Thanks to popular hardware leaker rogame (_rogame), we know a few stuff about Rocket Lake. Starting off, it is known that Rocket Lake features the backport of 10 nm Willow Cove core, called Cypress Cove. That Cypress Cove is supposed to bring only 10% IPC improvements, according to the latest rumors.

With 10% IPC improvement the company will at least offer some more competitive product than it currently does, however, that should be much slower than 10 nm Tiger Lake processors which feature the original Willow Cove design. It shows that backporting of the design doesn't just bring loses of the node benefits like smaller design and less heat, but rather means that only a fraction of the performance can be extracted. Another point that rogame made is that Rocket Lake will run up to 5 GHz in boost, and it will run hot, which is expected.

JEDEC Publishes New DDR5 Standard for Advancing Next-Generation High Performance Computing Systems

JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced the publication of the widely-anticipated JESD79-5 DDR5 SDRAM standard. The standard addresses demand requirements being driven by intensive cloud and enterprise data center applications, providing developers with twice the performance and much improved power efficiency. JESD79-5 DDR5 is now available for download from the JEDEC website.

DDR5 was designed to meet increasing needs for efficient performance in a wide range of applications including client systems and high-performance servers. DDR5 incorporates memory technology that leverages and extends industry know-how and experience developing previous DDR memories. The standard is architected to enable scaling memory performance without degrading channel efficiency at higher speeds, which has been achieved by doubling the burst-length to BL16 and bank-count to 32 from 16. This revolutionary architecture provides better channel efficiency and higher application level performance that will enable the continued evolution of next-generation computing systems. In addition, the DDR5 DIMM has two 40-bit fully independent sub-channels on the same module for efficiency and improved reliability.

New features, such as DFE (Decision Feedback Equalization), enable IO speed scalability for higher bandwidth and improved performance. DDR5 supports double the bandwidth as compared to its predecessor, DDR4, and is expected to be launched at 4.8 Gbps (50% higher than DDR4's end of life speed of 3.2 Gbps).

xMEMS Launches Montara, World's First Monolithic True MEMS Speaker

Today xMEMS Labs emerged from stealth mode to reinvent sound with the introduction of Montara, the world's first monolithic true MEMS speaker, delivering high fidelity, full-bandwidth sound and low total harmonic distortion (THD) for sealed in-ear personal audio devices, including true wireless stereo (TWS) earbuds. Montara is also the world's first IP-57 rated microspeaker, enabling water and dust-resistant earbuds. Consumers will benefit from enhanced audio fidelity with raised levels of clarity and detail for instruments and vocals, extremely low latency, waterproof earbuds, and longer listening times.

"With on-the-go media consumption on the rise such as subscription music, podcasts, video, audiobooks and mobile gaming, consumers are increasingly demanding enhanced audio quality and extended listen times between charges," said Joseph Jiang co-founder and CEO. "Until now, the industry has relied on antiquated, centuries-old multi-component voice coil speakers requiring labor-intensive, high variability factory assembly lines. Our revolutionary Montara product is a game changer for delivering a new combination of audio fidelity, size, energy consumption and uniformity not possible with traditional voice coil approaches."

Arm Announces new IP Portfolio with Cortex-A78 CPU

During this unprecedented global health crisis, we have experienced rapid societal changes in how we interact with and rely on technology to connect, aid, and support us. As a result of this we are increasingly living our lives on our smartphones, which have been essential in helping feed our families through application-based grocery or meal delivery services, as well as virtually seeing our colleagues and loved ones daily. Without question, our Arm-based smartphones are the computing hub of our lives.

However, even before this increased reliance on our smartphones, there was already growing interest among users to explore the limits of what is possible. The combination of these factors with the convergence of 5G and AI, are generating greater demand for more performance and efficiency in the palm of our hands.
Arm Cortex-A78

Arm Offers Startups Zero-cost Access to its IP Portfolio

Arm today announced the launch of Arm Flexible Access for Startups, an extension of its already highly successful Flexible Access program. This new initiative offers early-stage silicon startups zero-cost access to a huge range of Arm's leading IP, along with global support and training resources, enabling them to start on their journey to commercial silicon and business scale.

"In today's challenging business landscape, enabling innovation is critical - now more than ever, startups with brilliant ideas need the fastest, most trusted route to success and scale," said Dipti Vachani, senior vice president and general manager, Automotive and IoT Line of Business, Arm. "Arm Flexible Access for Startups offers new silicon entrants a faster, more cost-efficient path to working prototypes, resulting in strengthened investor confidence for future funding."
Arm Chip

Source Code of CS: GO and Team Fortress 2 Leaks

Source Code of Counter-Strike: Global Offensive and Team Fortress 2 got leaked today. It seems like Valve hasn't been careful with control of its output, and a few leaks came out. All of the licensees of the Source Engine, a multi-platform game engine used in all Valve's games like Dota 2, Half-Life, and CS: GO, have been empowered by Valve with access to the source code of 2017/2018 versions of CS: GO and Team Fortress 2. Someone down the line, however, took that opportunity and access to leak the source code. The original news source is the SteamDB Twitter account, so we don't have any link to the actual source code.

This pretty big news since CS: GO can be considered as the most popular game on the Steam platform, and IP that Valve holds on it is very valuable. The 2017/2018 version that is leaked is probably outdated by a mile now, but it still represents an act of theft and should be treated as such. We are yet to see the response from Valve and how they will handle this situation.
Counter-Strike: Global Offensive source code

New Philips ActionFit Wireless Sports Earbud with UV Cleaning Technology

Envision Peripherals, Inc. (EPI), the sole distributor of Philips-branded monitors and audio products in North America, today announces an addition to the Philips audio line with the Philips ActionFit Wireless Earbud with ultraviolet (UV) cleaning technology (TAST702BK/00). The earbuds harbor a compact soak resistant design, clear sound and comfortable fit. The Philips ActionFit Wireless Earbuds are now available on Amazon, for $179.99 USD. [Editor's note: The product appears to already be on sale for $139.99 on Amazon at this time.]

"Active people today need a quality audio solution that fits their lifestyles. The new Philips TAST702s are the perfect solution to take to the gym or go on a long bike ride, because of their comfort and their hygienic features," said David Ray, Director of Marketing for EPI.

DDR5 Arrives at 4800 MT/s Speeds, First SoCs this Year

Cadence, a fabless semiconductor company focusing on the development of IP solutions and IC design and verification tools, today posted an update regarding their development efforts for the 5th generation of DDR memory which is giving us some insights into the development of a new standard. The new DDR5 standard is supposed to bring better speeds and lower voltages while being more power-efficient. In the Cadence's blog called Breakfast Bytes, one of Cadence's memory experts talked about developments of the new standards and how they are developing the IP for the upcoming SoC solutions. Even though JEDEC, a company developing memory standards, hasn't officially published DDR5 standard specifications, Cadence is working closely with them to ensure that they stay on track and be the first on the market to deliver IP for the new standard.

Marc Greenberg, a Cadence expert for memory solutions was sharing his thoughts in the blog about the DDR5 and how it is progressing. Firstly, he notes that DDR5 is going to feature 4800 MT/s speeds at first. The initial speeds will improve throughout the 12 months when the data transfer rate will increase in the same fashion we have seen with previous generation DDR standards. Mr. Greenberg also shared that the goals of DDR5 are to have larger memory dies while managing latency challenges, same speed DRAM core as DDR4 with a higher speed I/O. He also noted that the goal of the new standard is not the bandwidth, but rather capacity - there should be 24Gb of memory per die initially, while later it should go up to 32Gb. That will allow for 256 GB DIMMs, where each byte can be accessed under 100 ns, making for a very responsive system. Mr. Greenberg also added that this is the year of DDR5, as Cadence is receiving a lot of orders for their 7 nm IP which should go in production systems this year.
Cadence DDR5

AMD Reports Theft of Graphics IP, Stolen Information Not Core to Competitiveness

AMD today disclosed that in December 2019, it was contacted by a person in possession of test files related to development of future graphics products, some of which were posted online and later taken down. This person has additional files that were never posted online, but the company maintains the data breach won't affect the competitiveness or security of its upcoming graphics processors. The company said that it is working closely with law enforcement as part of a criminal investigation into the incident.

The statement by AMD follows:
At AMD, data security and the protection of our intellectual property are a priority. In December 2019, we were contacted by someone who claimed to have test files related to a subset of our current and future graphics products, some of which were recently posted online, but have since been taken down. While we are aware the perpetrator has additional files that have not been made public, we believe the stolen graphics IP is not core to the competitiveness or security of our graphics products. We are not aware of the perpetrator possessing any other AMD IP. We are working closely with law enforcement officials and other experts as a part of an ongoing criminal investigation.

Intel Rocket Lake-S Platform Detailed, Features PCIe 4.0 and Xe Graphics

Intel's upcoming Rocket Lake-S desktop platform is expected to arrive sometime later this year, however, we didn't have any concrete details on what will it bring. Thanks to the exclusive information obtained by VideoCardz'es sources at Intel, there are some more details regarding the RKL-S platform. To start, the RKL-S platform is based on a 500-series chipset. This is an iteration of the upcoming 400-series chipset, and it features many platform improvements. The 500-series chipset based motherboards will supposedly have an LGA 1200 socket, which is an improvement in pin count compared to LGA 1151 socket found on 300 series chipset.

The main improvement is the CPU core itself, which is supposedly a 14 nm adaptation of Tiger Lake-U based on Willow Cove core. This design is representing a backport of IP to an older manufacturing node, which results in bigger die space due to larger node used. When it comes to the platform improvements, it will support the long-awaited PCIe 4.0 connection already present on competing platforms from AMD. It will enable much faster SSD speeds as there are already PCIe 4.0 NVMe devices that run at 7 GB/s speeds. With RKL-S, there will be 20 PCIe 4.0 lanes present, where four would go to the NVMe SSD and 16 would go to the PCIe slots from GPUs. Another interesting feature of the RKL-S is the addition of Xe graphics found on the CPU die, meant as iGPU. Supposedly based on Gen12 graphics, it will bring support for HDMI 2.0b and DisplayPort 1.4a connectors.
Intel Rocket Lake-S Platform

Xilinx Announces World's Highest Bandwidth, Highest Compute Density Adaptable Platform for Network and Cloud Acceleration

Xilinx, Inc. today announced Versal Premium, the third series in the Versal ACAP portfolio. The Versal Premium series features highly integrated, networked and power-optimized cores and the industry's highest bandwidth and compute density on an adaptable platform. Versal Premium is designed for the highest bandwidth networks operating in thermally and spatially constrained environments, as well as for cloud providers who need scalable, adaptable application acceleration.

Versal is the industry's first adaptive compute acceleration platform (ACAP), a revolutionary new category of heterogeneous compute devices with capabilities that far exceed those of conventional silicon architectures. Developed on TSMC's 7-nanometer process technology, Versal Premium combines software programmability with dynamically configurable hardware acceleration and pre-engineered connectivity and security features to enable a faster time-to-market. The Versal Premium series delivers up to 3X higher throughput compared to current generation FPGAs, with built-in Ethernet, Interlaken, and cryptographic engines that enable fast and secure networks. The series doubles the compute density of currently deployed mainstream FPGAs and provides the adaptability to keep pace with increasingly diverse and evolving cloud and networking workloads.
Xilinx Versal ACAP FPGA

Rambus Designs HBM2E Controller and PHY

Rambus, a maker of various Interface IP solutions, today announced the latest addition to its high-speed memory interface IP product portfolio in form of High Bandwidth Memory 2E (HBM2E) controller and physical layer (PHY) IP solution. The two IPs are enabling customers to completely integrate the HBM2E memory into their products, given that Rambus provides a complete solution for controlling and interfacing the memory. The design that Ramus offers can support for 12-high DRAM stacks of up to 24 Gb devices, making for up to 36 GB of memory per 3D stack. This single 3D stack is capable of delivering 3.2 Gbps over a 1024-bit wide interface, delivering 410 GB/s of bandwidth per stack.

The HBM2E controller core is DFI 3.1 compatible and has support for logic interfaces like AXI, OCP, or a custom one, so the customer can choose a way to integrate this core in their design. With a purchase of their HBM2E IP, Rambus will provide source code written in Hardware Description Language (HDL) and GDSII file containing the layout of the interface.

CEA-Leti Makes a 96 core CPU from Six Chiplets

Chiplet design of processors is getting more popular due to many improvements and opportunities it offers. Some of the benefits include lower costs as the dies are smaller compared to one monolithic design, while you are theoretically able to stitch as much of the chiplets together as possible. During the ISSCC 2020 conference, CEA-Leti, a French research institute, created a 96 core CPU made from six 3D stacked 16 core chiplets. The chip is created as a demonstration of what this modular approach offers and what are the capabilities of the chiplet-based CPU design.

The chiplets are manufactured on the 28 nm FD-SOI manufacturing process from STMicroelectronics, while the active interposer die below them that is connecting everything is made using the 65 nm process. Each one of the six dies is housing 16 cores based on MIPS Instruction Set Architecture core. Each chiplet is split into four 4-core clusters that make up for a total of 16 cores per chiplet. When it comes to the core itself, it is a scalar MIPS32v1 core equipped with 16 KiB of L1 instruction and an L1 data cache. For L2 cache, there is 256 KiB per cluster, while the L3 cache is split into four 1 MiB tiles for the whole cluster. The chiplets are stacked on top of an active interposer which connects the chiplets and provides external I/O support.

SK Hynix Licenses DBI Ultra 3D Interconnect Technology

Xperi Corporation today announced that it entered into a new patent and technology license agreement with SK hynix, one of the world's largest semiconductor manufacturers. The agreement includes access to Xperi's broad portfolio of semiconductor intellectual property (IP) and a technology transfer of Invensas DBI Ultra 3D interconnect technology focused on next-generation memory.

"We are delighted to announce the extension of our long-standing relationship with SK hynix, a world-renowned technology leader and manufacturer of memory solutions," said Craig Mitchell, President of Invensas, a wholly owned subsidiary of Xperi Corporation. "As the industry increasingly looks beyond conventional node scaling and turns toward hybrid bonding, Invensas stands as a pioneering leader that continues to deliver improved performance, power, and functionality, while also reducing the cost of semiconductors. We are proud to partner with SK hynix to further develop and commercialize our DBI Ultra technology and look forward to a wide range of memory solutions that leverage the benefits of this revolutionary technology platform."

Arm Delivers New Edge Processor IPs for IoT

Today, Arm announced significant additions to its artificial intelligence (AI) platform, including new machine learning (ML) IP, the Arm Cortex -M55 processor and Arm Ethos -U55 NPU, the industry's first microNPU (Neural Processing Unit) for Cortex-M, designed to deliver a combined 480x leap in ML performance to microcontrollers. The new IP and supporting unified toolchain enable AI hardware and software developers with more ways to innovate as a result of unprecedented levels of on-device ML processing for billions of small, power-constrained IoT and embedded devices.

Intel joins CHIPS Alliance to promote Advanced Interface Bus (AIB) as an open standard

CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced industry leading chipmaker Intel as its newest member. Intel is contributing the Advanced Interface Bus (AIB) to CHIPS Alliance to foster broad adoption.

CHIPS Alliance is hosted by the Linux Foundation to foster a collaborative environment to accelerate the creation and deployment of open SoCs, peripherals and software tools for use in mobile, computing, consumer electronics and Internet of Things (IoT) applications. The CHIPS Alliance project develops high-quality open source Register Transfer Level (RTL) code and software development tools relevant to the design of open source CPUs, SoCs, and complex peripherals for Field Programmable Gate Arrays (FPGAs) and custom silicon.

Audio-Technica Also Introduces Upgraded SonicSport Wireless In-Ear Headphones

Audio-Technica is also introducing two SonicSport wireless Bluetooth in-ear headphones. The ATH-SPORT90BT features a built-in music player for the ultimate in on-the-go listening convenience and along with the ATH-SPORT60BT includes a number of useful upgrades from previous models. Both headphones offer a host of fitness-friendly features including IPX5 waterproof-rated construction, a built-in mic and controls for smartphone and portable device operation, and stay-in-place designs that keep them secure even during intense workouts. Both feature improved high-sensitivity drivers for impactful, immersive sound and offer longer battery life along with additional improvements.

Audio-Technica's SonicSport ATH-SPORT90BT (SRP: US$159.00) has newly-designed 6 mm drivers with a powerful magnetic circuit and dedicated headphone amplifier, to bring high-quality full-range (20 - 25,000 Hz) audio reproduction to listeners with active lifestyles. The ATH-SPORT90BT includes a built-in 4 GB music player, making it the ultimate portable music device - no need to carry a smartphone around during workouts. The headphones can also be paired with a smartphone or other Bluetooth device if desired.

Intel Acquires Artificial Intelligence Chipmaker Habana Labs

Intel Corporation today announced that it has acquired Habana Labs, an Israel-based developer of programmable deep learning accelerators for the data center for approximately $2 billion. The combination strengthens Intel's artificial intelligence (AI) portfolio and accelerates its efforts in the nascent, fast-growing AI silicon market, which Intel expects to be greater than $25 billion by 2024 (1).

"This acquisition advances our AI strategy, which is to provide customers with solutions to fit every performance need - from the intelligent edge to the data center," said Navin Shenoy, executive vice president and general manager of the Data Platforms Group at Intel. "More specifically, Habana turbo-charges our AI offerings for the data center with a high-performance training processor family and a standards-based programming environment to address evolving AI workloads."

Intel's AI strategy is grounded in the belief that harnessing the power of AI to improve business outcomes requires a broad mix of technology - hardware and software - and full ecosystem support. Today, Intel AI solutions are helping customers turn data into business value and driving meaningful revenue for the company. In 2019, Intel expects to generate over $3.5 billion in AI-driven revenue, up more than 20 percent year-over-year. Together, Intel and Habana can accelerate the delivery of best-in-class AI products for the data center, addressing customers' evolving needs.

AWS Starts Designing 32-Core Arm Neoverse N1 CPU for Data Center

Amazon Web Services, a part of Amazon that is in charge of all things cloud, has announced plans to release 32 core CPU based on Arm Neoverse N1 microarchitecture that is designed to handle a diverse workload that today's cloud infrastructure needs. This new CPU should be the second iteration of AWS'es custom CPU based on the Arm architecture. First-generation AWS CPU was a processor called Graviton, which Amazon offered on-demand in the cloud.

The still-unnamed second-gen CPU will utilize a 7 nm manufacturing process if the Neoverce N1 core at its base is to be believed. Additionally, everything from the Neoverse line should translate to this next-gen CPU as well, meaning that there will be features like high frequency and high single-threaded performance, cache coherency, and interconnect fabric designed to connect special-purpose accelerators to the CPU complex. For reference, Arm's design of Neoverce N1 has a TDP of 105 W for the whole SoC and its packs 64 cores running at 3.1 GHz, delivering amazing power efficiency and high core count.

GLOBALFOUNDRIES and SiFive to Deliver Next Level of High Bandwidth Memory on 12LP

GLOBALFOUNDRIES (GF ) and SiFive, Inc. announced today at GLOBALFOUNDRIES Technology Conference (GTC) in Taiwan that they are working to extend high DRAM performance levels with High Bandwidth Memory (HBM2E) on GF's recently announced 12LP+ FinFET solution, with 2.5D packaging design services to enable fast time-to-market for Artificial Intelligence (AI) applications.

In order to achieve the capacity and bandwidth for data-intensive AI training applications, system designers are challenged with squeezing more bandwidth into a smaller area while maintaining a reasonable power profile. SiFive's customizable high bandwidth memory interface on GF's 12LP platform and 12LP+ solution will enable easy integration of high bandwidth memory into a single System-on-Chip (SoC) solutions to deliver fast, power-efficient data processing for AI applications in the computing and wired infrastructure markets.
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