Intel's "Nova Lake-H" SoC, part of the Core Ultra 4000 Series, has reportedly surfaced. This is a second instance of "Nova Lake-H" surfacing, but this time without third-party annotations, and only coming with the raw, low-resolution SoC picture. This variant features a 4+8+4 configuration with 4 P-Cores, 8 E-Cores, and 4 LPE-Cores on a compute die made using Intel 18A-P technology. The package measures about 12x23 mm, resulting in a total die area of 276 mm², and includes both functional and dummy dies.

The first die is the graphics tile, built on the Intel 3-E node, embedding 4 Xe GPU cores and covering roughly 26 mm². Next to it is a dummy die occupying 21 mm², used for the structural integrity of the package. There is also a large 72 mm² die built on the Intel 18A-P node, hosting 4 LPE-Cores and serving as a central hub. Beside it is another 18A-P silicon die that functions as a peripheral control tile, measuring 58 mm². This configuration includes a compute tile, which hosts a 4P+8E-core configuration on the Intel 18A-P node, occupying 55 mm² of area.

Intel is moving some manufacturing capacity away from consumer chips to keep up with demand for its Xeon server processors. During its Q3 2026 earnings call, the company said it will convert some Intel 18A resources at its Oregon facilities to Intel 3, the node behind Xeon 6 "Granite Rapids." According to CFO Dave Zinsner, those 18A wafers "are generally going to build Panther Lake products." Zinsner also indicated that weaker PC demand gives Intel room to make the switch, as the company expects the PC slowdown to last at least through the first half of next year. CEO Lip-Bu Tan said the added Intel 3 capacity should be in production in the second half of 2027.

Intel CEO Lip-Bu TanThe industry continues to navigate one of the most significant supply shortages in the history, driven by the unprecedented demand for Super Intelligence. Against this backdrop, I am pleased by the progress we made growing our server supply in Q3. I'm mindful about the ongoing challenges we face in the future quarters to keep pace with the server demand.

During the Q3 2026 earnings call, Intel CEO Lip-Bu Tan confirmed that the company's upcoming flagship client CPU, codenamed "Nova Lake," will be produced by Intel Foundry using its 18A-P node. Initially, Intel planned to outsource the main compute tile production for "Nova Lake" to TSMC, utilizing its 2 nm N2 node. TSMC was expected to handle about 60-70% of the production, with the remainder produced in-house by Intel Foundry on the 18A node. This meant Intel would dual-source production for its next-generation chip. However, later supply chain information suggested that the company intended to bring the majority of "Nova Lake" compute tile production in-house, with these compute tiles being made on the Intel 18A-P node. Today, we received confirmation directly from the Intel CEO:

Intel CEO Lip-Bu Tan"Nova Lake," our first Intel 18A-P client product, is tracking ahead of schedule, with design wins expected to be twice those of "Panther Lake" at launch. We look forward to sharing more at CES in January.

Intel's upcoming "Nova Lake" lineup for mobile devices has been revealed in bare-die form, thanks to the Moore's Law Is Dead YouTube channel. Leading the lineup is the "Nova Lake-HX," featuring an 8+16+4 core configuration with 8 P-Cores, 16 E-Cores, and 4 LPE-Cores. The total silicon size measures 12x30 mm, amounting to 360 mm², which is divided across six different dies manufactured on various nodes. The first die is the graphics tile, built on the Intel 3-E node, embedding 4 Xe GPU cores and covering roughly 26 mm². Adjacent to it is a dummy die occupying 21 mm², used for the structural integrity of the package. Next, there is a large 72 mm² die built on the Intel 18A-P node, hosting 4 LPE-Cores and serving as a central hub. Beside it is another 18A-P silicon die that functions as a peripheral control tile, measuring 58 mm². Finally, Intel uses an external foundry for the main compute tile, which is on the TSMC N2P node and hosts the 8P+16E CPU core configuration. This compute tile occupies the largest area of 104 mm². Additionally, there is a passive tile next to it, with 85 mm² dedicated to the structural integrity of the package and the intended operation of the "Nova Lake-HX" chip.

Next, we move to the less powerful "Nova Lake-H" variant, which will feature a 4+8+4 configuration with 4 P-Cores, 8 E-Cores, and 4 LPE-Cores. This package is significantly smaller, measuring only 12x23 mm for a total die area of 276 mm², also consisting of both functional and dummy dies. The die configuration remains the same except for the main compute tile, which hosts a 4P+8E-core configuration on the TSMC N2P node, occupying 55 mm² of area. The adjacent passive die is also smaller, with an area of only 45 mm², while the peripheral control die, central hub die, and graphics tile are all made on Intel nodes and remain the same as in the "HX" variant.

Intel is reportedly preparing for a significant price increase across its silicon designs, according to supply chain sources cited by Commercial Times Taiwan. The first to experience this price hike is the latest "Panther Lake" processor generation, built on the Intel 18A node, with an increase ranging from 15% to 20% depending on the SKU. Intel reportedly made these adjustments on September 1, but consumer price increases have not yet been observed, or it may take a few more weeks for the old supply to clear. This supply-side price hike doesn't mean that Intel is directly changing its consumer pricing, but rather adjusting the pricing for major laptop OEMs such as Acer, ASUS, Lenovo, Dell, and HP. With a potential 20% price hike, this could translate to a few dozen US dollars more for the OEMs. Laptop manufacturers are likely to pass these increased costs onto consumers, especially given the current challenges with memory and storage pricing, which are already squeezing margins.

The reported price hikes don't stop there. The "Meteor Lake" and "Arrow Lake" processor families are also expected to see price increases, with reports indicating a 5% to 10% hike for these two generations, depending on the SKU. Intel sources silicon from both TSMC and its internal foundry, but the demand for silicon in the form of CPUs is skyrocketing in the age of AI, making price increases likely. Consumer demand remains, but much of the available CPU manufacturing capacity, both internally and externally, is being absorbed by agentic AI workloads, which are pushing server configurations to a 50:50 ratio of CPUs to GPUs.

SemiAnalysis has published a teardown of Intel's Panther Lake (Core Ultra 7 365), offering a rare look at 18A inside a shipping chip. Intel's 18A node brings advanced manufacturing technologies such as rear-side power delivery and a new transistor design, so its success is vital for the Foundry. The firm found the 18A compute logic to be similar in density to the TSMC N3E logic used in the 12-core Xe3 GPU tile. It also puts 18A about 18.6% denser than the Intel 3 GPU logic, using a representative-cell model. However, SemiAnalysis says 18A does not lead TSMC N3P, N2, or Samsung SF2 in peak density. It further cautions that whole-die density depends on cell mix and placement.

Panther Lake is Intel's first chip with RibbonFET gate-all-around transistors, and the first commercial implementation of PowerVia backside power delivery. SemiAnalysis counted four stacked ribbons per transistor, compared to three sheets on Samsung's SF2. Moreover, the Cougar Cove P-core takes roughly the same area as Lunar Lake's Lion Cove, even though L2 grew from 2.5 MiB to 3 MiB. Panther Lake's NPU 5 reportedly requires 36.9% less chip area than Lunar Lake's NPU 4, though the number of INT8 MAC units remains the same. SemiAnalysis describes the CPU cores as incremental updates.

Intel's Foundry chief, Naga Chandrasekaran, spoke with investment bank KeyBanc Capital Markets about Intel Foundry and the future trajectory of its nodes. One of the most intriguing insights is that Intel expects its 14A node to be within 5% of TSMC's A14 node, with both competing in the same sector. What this means exactly is unclear, as there are many factors by which a node is measured. These include transistor switching frequency, power efficiency, and density. The "within 5%" figure could imply a 5% advantage, a 5% disadvantage, or a mix of both, so the technical specifics remain uncertain. Intel's recent nodes, like the shipping 18A, are proving to be efficient and high-performing, but TSMC's nodes are also strong, with both companies continuing development.

Intel plans to start 14A node risk production in the second half of 2027, with high-volume production expected in 2028. The company has processed tens of thousands of 14A wafers in pilot production runs and is now working on yield improvements and minor node adjustments before beginning risk production next year. The 14A node is designed to offer a 15-20% performance improvement at the same power level compared to Intel 18A, or it can be optimized for a 25-35% power reduction at the same performance level. This will be accompanied by up to a 30% improvement in chip density compared to Intel 18A, though it is unclear if this refers to logic or SRAM scaling, as the latter has been challenging for the industry.

Intel Foundry might win the contract to manufacture base dies for HBM4E memory from SK hynix, according to the South Korean Herald. Reportedly, SK hynix is considering diversifying its base die supplier from solely TSMC to a dual sourcing strategy involving both TSMC and Intel, with Intel Foundry potentially securing a significant portion of the contract. As readers may recall, HBM4E memory allows for the implementation of a base die with custom logic, with DRAM dies stacked on top. Until now, SK hynix has only considered TSMC for this application, but now Intel is also being considered.

For instance, customers could implement custom logic like memory controllers and PHYs directly on the HBM4E base die, significantly reducing the area occupied by these components on the main compute chiplet. SK hynix would send the design to Intel, which would then provide these base dies to SK hynix. The South Korean memory giant would subsequently stack DRAM on top. This approach would free up space on the main compute tile in any AI accelerator for more processing units, reduce latency, and significantly improve performance. However, the question remains as to which Intel node would be used. Up until HBM3E, SK hynix used its own nodes to manufacture base dies. However, as those are 10 nm class nodes, customers are now requiring something more advanced.

Socionext Inc., a global leader in custom system-on-chip (SoC) design and advanced semiconductor solutions, announced that it will leverage Intel 18A-P process technology in the development of custom SoCs that meet the emerging needs of datacenter, edge, and high-performance computing customers. The first development is a high-performance compute chiplet.

By combining its ASIC expertise with Intel Foundry's advanced process and packaging roadmap, Socionext will enable customers to create differentiated SoC solutions optimized for application-specific workloads. "Intel 18A-P represents an important step in advanced process technology, combining innovations in transistor architecture and power delivery," said Rajinder Cheema, CTO and Executive Vice President at Socionext. "By developing SoC capabilities on this process, Socionext is enabling our customers to address the evolving performance and power requirements of AI, HPC, and advanced datacenter applications."

According to the latest information shared by long-time Intel leaker Jaykihn, Intel's upcoming Xeon 7 "Diamond Rapids" will feature a flagship SKU with up to 256 P-Cores. This contradicts previous reports suggesting that Intel's flagship Xeon 7 SKU would be limited to 192 P-Cores and 192 threads, as this generation does not include Hyper-Threading. From Intel's VLSI Symposium 2026 presentation, we learned that "Diamond Rapids" includes four Compute tiles, also known as "core building blocks" (CBBs), each built on the Intel 18A-P foundry node. Each Compute tile contains a CPU complex with 48 "Panther Cove" P-Cores and an L3 cache localized to the tile. However, a 256-core design implies CBBs with 64 cores each and possibly a larger L3 cache.

Using Intel's latest 18A-P node, the "Diamond Rapids" CBBs are expected to achieve a 9% increase in performance at the same power level compared to the standard 18A node, or an 18% power reduction at the same performance level. Since Intel aims for maximum performance, we can expect these improvements to enhance performance further or to optimize power consumption with the additional cores. Earlier claims suggested a 500 W TDP design for 192 P-Core version, featuring 16 DDR5 memory channels and running on a new LGA-9324 socket on the "Oak Stream" platform. However, a 256-core design could go much higher, and cooling manufacturers have indicated 800+ W TDP designs for this socket.

For decades, defense and aerospace systems have relied on architectures that were not designed for today's data intensity. Analog-heavy signal-processing chains, while effective in earlier generations of radar and sensing systems, pose inherent limitations on scalability, flexibility, and efficiency. As sensor resolution increases, particularly in applications such as phased array radar and infrared imaging, the volume of data grows exponentially, placing unsustainable demands on both processing and power.

At the same time, these systems must operate within fixed SWaP (size, weight, and power) operational limits. In aircraft, power is a shared and finite resource, with competing subsystems drawing from the same limited supply, making it the most constrained resource on the platform. In space-based systems, the challenge is even more acute: power generation is hampered, and thermal dissipation is intrinsically difficult in vacuum environments where conventional cooling methods are unavailable.

Cadence's AI-driven digital and custom reference flows, tools, and solutions are now certified on Intel 18A-P and Intel 14A technologies, based on the latest Intel Foundry process design kits (PDKs). Building on the companies' recent expansion of design IP optimized for Intel 18A and 18A-P and their multi-year Design Technology Co-Optimization (DTCO) agreement targeting Intel 14A, this new certification provides customers with a signoff-ready path to deploy advanced AI, high performance computing (HPC), and mobile SoCs on Intel Foundry's leading-edge nodes.

Cadence has worked closely with Intel Foundry to co-optimize tools, flows, and methodologies that fully leverage the innovations in Intel 18A, Intel 18A-P, and Intel 14A, including RibbonFET gate-all-around transistors and advanced backside power delivery technologies such as PowerVia and PowerDirect. By tightly coupling process capabilities with Cadence's agentic AI-driven EDA portfolio and high-performance design IP, customers can achieve industry-leading power, performance, and area (PPA) while reducing design risk and time to market.

ASML Holding N.V. (ASML) today reported that Intel Foundry is using ASML's High NA EUV technology on the Intel 18A process node to produce a subset of its Intel Core Ultra Series 3 processors. This milestone marks an important step in demonstrating High NA EUV readiness in a production environment. ASML and Intel have worked closely for decades to advance lithography technology and support the continued scaling of semiconductors. The high numerical aperture extreme ultraviolet (High NA EUV) lithography process is an important next step in EUV lithography, developed by ASML to enable more precise patterning for advanced chip manufacturing.

The Intel Core Ultra Series 3 processors, code-named Panther Lake, are built on Intel 18A. The use of High NA EUV to pattern specific layers of these products provides ASML and Intel Foundry with helpful data to further refine system setup, up time and manufacturing implementation. This paves the way towards broader adoption, utilizing the full capabilities of the technology.

Intel's 18A node is officially space-grade, according to documentation on Intel's website. A document that initially went unnoticed has been published, detailing a new "Starfire" generation of processors built on the 18A node and designed for space operations. Intel has designated two SKUs for orbital computing, each equipped with four P-Cores and four LPE-Cores, resulting in an eight-core SoC design. One is optimized for low-power operations with clocks adjusted for efficiency, while the other is designed for performance. The Low Power edition tunes its four P-Cores to 1.0 GHz, while the four LPE-Cores run at 850 MHz. For the Performance version, Intel has increased the frequency of P-Cores to 3.1 GHz, with LPE-Cores reaching up to 2.1 GHz.

Both SKUs feature a GPU tile built on the Intel 3 node, which includes 4 Xe cores with 64 EUs. On the Low Power SKU, these Xe cores operate between 800 MHz and 1.0 GHz, while the Performance SKU boosts this to 2.0 GHz. The total package for the Low Power version remains at 10 W TDP, while the Performance SKU is capped at 35 W TDP. Additionally, Intel includes an NPU on both versions, with a compute capability of 45 TOPS on the Low Power version and up to 75 TOPS on the Performance SKU using INT8 precision. Beyond specifications, "Starfire" can operate within a T-Junction range from -55°C to 125°C. This range, alongside TID, SEL, and SEE radiation hardening certifications, introduces the first 18A silicon to space, ideal for orbital computation. Intel targets this quarter, Q3, for samples.

Intel Corporation today announced the appointment of Seok-Hee Lee as executive vice president of Intel Foundry, reporting directly to CEO Lip-Bu Tan. In this role, Lee will lead all advanced packaging, system integration, back-end technology development, and back-end manufacturing, strengthening Intel's ability to deliver differentiated, system-level innovation for customers.

Seok-Hee Lee Appointed to Lead Advanced Packaging
As part of the continued evolution of the Intel Foundry strategy, the company is establishing advanced packaging as a focused business with dedicated leadership. This reflects the growing importance and complexity of packaging as a key enabler of performance, power efficiency, and heterogeneous integration across AI systems.

At the VLSI Symposium held in Hawaii, Intel unveiled the new Intel 18A-P foundry node, a significant refinement of the Intel 18A node that carves out room for a 9% increase in performance at iso-power. The company announced that it commenced risk-production on this new node, and has earmarked it for its next-generation Xeon "Diamond Rapids" server processor. Besides 9% increase in performance at iso-power, Intel 18A-P is claimed to offer an 18% power reduction at iso-performance, a 20-40% improvement in die-level thermal resistance, and a 10-30% improvement in Via resistance in performance-critical layers.

The company detailed the physical changes to the Intel 18A node made to achieve these gains. Intel added new cell options across its 180HP and 160HD libraries to support a wider range of products. For low-power designs, it introduced W1 and W1.5 cells. For high-performance needs, it added the W3P cell, which utilizes a "dual contact" design to boost performance without exceeding the footprint of the existing W3 cell. The company significantly lowered thermal resistance by integrating a new heat-conducting material on the front side of the die. Intel also updated its EDA tools to support thermally-aware layouts, allowing designers to better manage heat dissipation at the structural level.

Intel is planning a new line of processors featuring integrated graphics solutions by NVIDIA, according to a report by tech journalist Erdi Özüağ. The company is planning to introduce these processors by CES 2028. There are no details on what the processor will be. Intel has, in the past, sourced big integrated GPUs from third-party vendors. For example, the 7th Gen Core "Kaby Lake-G," a limited production-run mobile processor that paired a 4-core "Kaby Lake" CPU die with an AMD Radeon RX Vega M GPU on a multi-chip module.

Fast-forward to today, and there are several approaches Intel could take to developing such a chip. Given that it makes tile-based disaggregated client processors with SoC tiles made on TSMC nodes, it's possible that this chip could be a "Panther Lake" or "Nova Lake" derivative that combines Compute and a truncated SoC tile from Intel; with a GPU tile from NVIDIA. Unlike Intel's own Graphics tile, the NVIDIA tile could also integrate display engines and media accelerators. In related news, Özüağ says that Apple is in advanced stages of consultation with Intel over using its Intel 18A foundry node for manufacturing of some of its Apple Silicon products.

Intel today formally launched the Arc G3 series, a series of fully-integrated SoCs for gaming handhelds out to compete with AMD Ryzen Z-series. Intel felt the need for such a product line when it observed OEMs using U-segment mobile processors for handheld consoles. The Arc G3 features a tailored balance of CPU compute, and graphics muscle, generally favoring the latter, with power management that's fine-tuned for typical handheld gaming use-cases. This time around, Intel also made the effort to co-engineer devices with OEMs so their battery-life and thermals have knowhow from Intel.

Intel tapped into its latest "Panther Lake" microarchitecture to create the Arc G3 series. The company claims performance up to 42% higher than the competition (being AMD Ryzen Z2 Extreme based on "Strix Point"); with as much as 11 hours of gameplay on battery, and support for XBOX mode. It also brings the full stack of Intel Arc innovations such as XeSS 3 upscaling, frame-generation, and low-latency, the GPU provides full DirectX 12 Ultimate acceleration. Also on the software side, the console gets day-0 game optimization from Intel, along with pre-compiled shaders. Intel also brings segment-first connectivity features such as Thunderbolt 4 and Wi-Fi 7.

Intel today announced a series of data center advancements, including new Intel Xeon 6+ processors, an expanded 800 Series Ethernet portfolio featuring the Intel Ethernet E835 controllers and network adapters, and continued progress on its AI accelerator roadmap, including updates on Crescent Island. Together, these developments highlight a clear industry shift: as AI becomes more agentic, the CPU is re-emerging at the center of modern AI infrastructure. With Xeon serving as the control plane, Intel is taking a systems-level approach to performance and efficiency at scale—delivering platforms designed for increasingly agentic AI workloads, where orchestration, data movement, and sustained inference are critical across data center and network environments.

"AI doesn't scale as a collection of parts—it scales as a coordinated system," said Kevork Kechichan, executive vice president and general manager of Intel Data Center Group. "As AI becomes more agentic, the constraints shift to orchestration, concurrency, and data movement. That shift reinforces a core reality: the CPU remains the control plane for the modern AI infrastructure. With Xeon 6+ and Ethernet E835, we're tightly coupling compute and networking to reduce bottlenecks and enable efficient, secure scaling of real-world agentic workflows."

As edge AI adoption accelerates across the commercial market, GIGABYTE Technology, a global leader in high-performance computing, today announced the new GB-BRU9-386H for its BRIX Mainstream ultra-compact mini PC series—expanding its enterprise on-premises AI portfolio. Powered by Intel Core Ultra Series 3 processors and manufactured on the Intel 18A process node technology, the new system delivers up to 75% higher NPU performance than the previous generation, reaching up to 50 TOPS to accelerate AI inference and improve overall computing efficiency.

Staying true to BRIX's compact design, the latest BRIX Mainstream packs a 0.46-liter chassis with an ultra-slim 35 mm profile for easy deployment in space-constrained environments. Built for real-world business needs—from retail and industrial automation to surveillance and medical imaging—it delivers high performance, low latency, and privacy-preserving on-site computing at edge, helping organizations turn AI use cases into operational outcomes faster.

Beelink has officially introduced its first product lineup based on Intel's latest Wildcat Lake low-power platform, bringing next-generation performance, AI capabilities and efficiency to compact desktop systems. The new series includes two mini PCs and one NAS-oriented device, making Beelink the first tech brand to deploy Wildcat Lake across multiple product categories.

Intel 18A: A Fundamental Leap
At the core of the platform is Intel's advanced 18A process technology. The new node introduces RibbonFET gate-all-around transistors and PowerVia backside power delivery, significantly improving power efficiency, thermal performance, and signal stability compared to previous FinFET-based designs. Combined with Intel's new Cougar Cove performance cores and Darkmont efficiency cores, Wildcat Lake delivers higher performance at lower power consumption.

CHUWI today unveiled the UniBook, the world's first laptop powered by Intel's Wildcat Lake Core 3 304 processor (Core Series 3, Intel 18A, 5 cores/5 threads, up to 4.30 GHz). Primarily targeted for university students, entrepreneurs, and young professionals, the battery life can reach 15-20 hours (under comprehensive working conditions). Starting at an estimated $449, the UniBook directly challenges Apple's MacBook Neo with clear advantages in connectivity, keyboard backlight, display color accuracy, and price.

Key specs for CHUWI UniBook: 14-inch FHD (1920 x 1200) 100% sRGB IPS display, 8 GB LPDDR5X, 256 GB PCIe 3.0 SSD, Wi-Fi 6 + BT5.2, a full port suite (2x full-function USB-C, 1x HDMI 2.0, 2x USB 3.2 Gen 1, 1x USB 2.0, Gigabit Ethernet, TF card slot, 3.5 mm audio), white backlit keyboard, 180-degree hinge, active cooling, 53.38 Wh battery, and Windows 11 Pro.The specifications follow.

According to the sell-side equity research firm GF Securities, Apple is set to utilize both Intel's 18A-P and 14A nodes for its product lineups. As previously reported, the company will employ Intel's advanced 18A-P node for the M7 SoCs that power MacBook Air and entry-level MacBook Pro laptops. Intel's investment in the development and manufacturing ramp of the 14A node will also be beneficial, as Apple plans to use the 14A node for producing A21 SoCs for iPhones. The 18A-P node is ideal for Apple's laptop SoCs, providing a balance between efficiency and speed. It offers a 9% performance increase at the same power level or achieves 18% power savings at the same performance level compared to the standard 18A node, resulting in laptops with good frequency and low power usage. With Apple moving away from TSMC's 3 nm node in the current M5 SoC, the improvements will be significant and are expected to be realized by 2027.

For the A21 iPhone SoCs, Apple will use Intel's advanced 14A node, which promises a generational leap in density, frequency, and power savings. Apple's primary goal is to employ a more advanced node for mobile devices, with plans to have these chips ready by 2028. As this is anticipated to begin in about two years, Apple will likely wait for the final 14A PDK before starting trial production. It remains uncertain whether the company will manufacture its A21 Pro SoC at TSMC and leave the regular version to Intel. However, Apple is gradually diversifying its supply chain with more silicon manufacturers. With advanced packaging, Intel can compete with TSMC in many areas, and we are eager to see the outcomes of this competition.

Apple and Intel Foundry Services have reached a preliminary agreement to onboard Apple as a foundry customer for manufacturing of Apple Silicon on its latest foundry nodes, according to a Wall Street Journal report. The move could see Apple end its near-total reliance on TSMC for production of its chips. Apple is looking to leverage the Intel 18A foundry node that offers comparable transistor densities and electric characteristics as TSMC's 2 nm-class nodes. Intel manufactures chips on the Intel 18A node in the state of Oregon, and is building new facilities in Ohio that will cater to future nodes. The company also has chip packaging facilities in states such as Arizona and Nevada. The move could improve Apple's contribution to the U.S. Government's efforts to onshore manufacturing of chips and other strategic commodities.

Companies like Apple are always seeking top-tier manufacturing for their Apple Silicon products, which range from the A-Series chips in iPhones and low-power MacBooks to the more powerful M-Series SoCs that power iPads and higher-end Macs. Manufacturing these custom processors has traditionally been handled by TSMC, but Bloomberg now reports that Apple has been in talks with both Intel Foundry and Samsung Foundry to manufacture some of its chips in the coming months. It has been known for some time that Apple is exploring Intel's 18A-P process design kits (PDKs). Apple has used version 0.9.1 of the PDK designed for Intel's 18A-P node. With performance, density, power, and other metrics meeting expectations, Intel could become Apple's source for advanced node production by 2027.

Additionally, Apple is reportedly waiting for Intel to release the 18A-P PDK version 1.0, which is on track to launch in the first half of 2026 or may have already been released to partners. Once available, Apple plans to start with the lowest-end M-series chip, used in MacBook Air and iPad Pro devices, as previously mentioned. This node is particularly interesting due to its performance characteristics, as the 18A-P can deliver a 9% performance increase at the same power level or achieve 18% power savings at the same performance level compared to the standard 18A. This is exactly what Apple is looking for. Coupled with better thermal conductivity, these designs should offer improved heat dissipation and performance compared to what Apple currently achieves with TSMC's 3 nm process in the M5 SoC.