Intel has quietly rolled out three new Arrow Lake processors as part of its Ultra 5 lineup, enhancing its entry-level options with the Ultra 5 235A, 235TA, and 235UA models. The Ultra 5 235A and 235TA processors are quite similar, both featuring a total of 14 cores—six of which are performance cores and eight are efficient cores with 14 threads. They can both reach turbo frequencies of 5 GHz on their performance cores, while the efficient cores can go up to 4.4 GHz. The main difference between the two CPUs is the power consumption and base frequencies. The Ultra 5 235A runs at 65 W with its performance cores clocking at a base frequency of 3.4 GHz. The Intel Ultra 5 235TA is designed to be more power-efficient, operating at just 35 W with its performance cores running at a base frequency of 2.2 GHz. Both of these desktop models are built using TSMC's N3B manufacturing process and come equipped with 24 MB of Smart Cache.

Update 19:03 UTC:
The Ultra 5 235UA has an identical device ID to the Ultra 7 265U, a Meteor Lake based CPU that uses Redwood Cove P-Cores and Crestmont E-Cores, thus, the CPU does actually have 12 cores and 14 threads, due to the two P-Cores offering Hyper-Threading, which was removed in Arrow Lake's Lion Cove P-Core design, for security, area efficiency, and performance reasons. This is quite confusing, since the product is marketed as an Arrow Lake "Series 2" CPU, but is actually based on the preceding mobile only Meteor Lake "Series 1" architecture. The only differences between the 235UA/265U and the Meteor Lake 165U is the process node the chip is built on, with the 165U being fabbed on Intel 4, and the 265U/235UA refresh chips being fabbed on Intel 3, which allows for a slight clock speed bump within the same power budget.

Die shots of Intel's "Arrow Lake" desktop processors have appeared online, confirming the chiplet design we have known about since the launch. The images annotated by the YouTube channel HighYield show a four‑tile arrangement mounted on a base die made with Intel's 22 nm FinFET process. The compute tile sits at the top left, built on TSMC's N3B node and covering 117.24 mm². To its right are the SoC tile on TSMC's N6 node measuring 86.65 mm², and the GPU tile, which houses four Xe cores alongside an Arc Alchemist render slice. The I/O tile, at 24.48 mm² on the same N6 node, completes the group at the bottom left. Intel has redesigned its hybrid core layout for Arrow Lake, moving away from separate P‑core and E‑core clusters. Four of the eight high‑performance P‑cores line the die's outer edges, with the remaining four in the center. In between these lie the four efficiency E‑core clusters, each sharing 3 MB of L2 cache. A unified 36 MB L3 cache ring bus connects to every core, allowing E‑cores to tap into that larger cache pool for the first time. Intel aims to spread heat more evenly and boost background task performance.

The I/O tile integrates Thunderbolt 4 controllers, PCIe buffers and PHYs. The SoC tile carries display engines, media accelerators and DDR5 memory controllers. All tiles are bonded to the base die via Intel's Foveros Omni stacking technology. Arrow Lake also reflects a shift in Intel's manufacturing strategy. Plans to use Intel's 20A node were dropped in favor of TSMC processes, making this the first desktop CPU from Intel that relies almost entirely on external foundries. On the software side, Intel has begun offering its IPO profiles in select prebuilt systems. These presets optimize CPU and memory settings for a hassle‑free performance boost that remains within warranty limits. Meanwhile, the native 200S Boost overclocking option is rolling out via BIOS updates. Early tests suggest that 200S Boost alone yields modest gains unless paired with very high-speed DDR5 modules, while IPO profiles deliver more consistent improvements with mainstream memory configurations.

Intel's Core Ultra 7 255H "Arrow Lake" processor has demonstrated impressive performance improvements in recent PassMark benchmarks, achieving a 32% higher single-core score compared to its "Meteor Lake" predecessor. The Arrow Lake-H chip recorded 4,631 points in single-threaded tests, significantly outpacing the Core Ultra 7 155H's 3,500 points while delivering a 15% overall improvement in CPU Mark ratings. The performance leap comes from Intel's architectural overhaul, implementing "Lion Cove" performance cores alongside "Skymont" efficiency cores on TSMC's N3B process node. This combination enables the 255H to achieve higher boost frequencies while maintaining the same core configuration as its predecessor—six P-cores, eight E-cores, and two Low Power Efficiency (LPE) cores.

Notable in this iteration is the absence of Hyper-Threading, resulting in 16 threads compared to the 155H's 22 threads. Arrow Lake-H maintains Intel's heterogeneous structure, incorporating up to eight Xe-LPG+ graphics cores derived from the Alchemist architecture. The neural processing unit (NPU) capabilities remain consistent with Meteor Lake, delivering 13 TOPS of INT8 performance. This positions the chip below Lunar Lake's 45 TOPS. Despite performance improvements, market success will largely depend on system integrators' ability to deliver compelling devices at competitive price points, particularly as AMD's Strix Point platforms maintain strong positioning in the $1,000 range. The battle of laptop chip supremacy is poised to be a good one in the coming quarters, especially as more Arm-based entries will force both Intel and AMD to compete harder.

Samsung's latest semiconductor manufacturing technology is falling short of expectations, as the company struggles to achieve acceptable production rates for its cutting-edge 3 nm chips. The latest rumors indicate that both versions of Samsung's 3 nm Gate-All-Around (GAA) process produce fewer viable chips than anticipated. The initial targets set by the South Korean tech giant were aimed at a 70% yield rate in volume production. However, the first "SF3E-3GAE" iteration of the technology has only managed to achieve between 50-60% viable yield output. More troubling is the performance of the second-generation process, which is reportedly yielding only 20% of usable chips—a figure that falls dramatically short of production goals. The timing is particularly challenging for Samsung as major clients begin to reevaluate their manufacturing partnerships.

Qualcomm has opted to produce its latest Snapdragon 8 Elite processors exclusively through rival TSMC's 3 nm facilities. Even more telling is the exodus of South Korean companies, traditionally loyal to Samsung, who are now turning to TSMC's more reliable manufacturing processes. While Samsung can claim the achievement of bringing 3 nm GAA technology to market before TSMC's competing N3B process, this technical victory rings hollow without the ability to mass-produce chips efficiently. The gap between Samsung's aspirations and manufacturing reality continues to widen. However, Samsung is shifting its focus toward its next technological milestone. Development efforts are reportedly intensifying around a 2 nm manufacturing process, with plans to debut this technology in a new Exynos processor (codenamed 'Ulysses') for the 2027 Galaxy S27 smartphone series.

As we witness Apple's generational updates of the M series of chips, the highly anticipated SKU of the 3rd generation of Apple M series yet-to-be-announced top-of-the-line M3 Ultra chip is growing speculations from industry insiders. The latest round of reports suggests that the M3 Ultra might step away from its predecessor's design, potentially adopting a monolithic architecture without the UltraFusion interconnect technology. In the past, Apple has relied on a dual-chip design for its Ultra variants, using the UltraFusion interconnect to combine two M series Max chips. For example, the second generation M Ultra chip, M2 Ultra, boasts 134 billion transistors across two 510 mm² chips. However, die-shots of the M3 Max have sparked discussions about the absence of dedicated chip space for the UltraFusion interconnect.

While the absence of visible interconnect space on early die-shots is not conclusive evidence, as seen with the M1 Max not having visible UltraFusion interconnect and still being a part of M1 Ultra with UltraFusion, industry has led the speculation that the M3 Ultra may indeed feature a monolithic design. Considering that the M3 Max has 92 billion transistors and is estimated to have a die size between 600 and 700 mm², going Ultra with these chips may be pushing the manufacturing limit. Considering the maximum die size limit of 848 mm² for the TSMC N3B process used by Apple, there may not be sufficient space for a dual-chip M3 Ultra design. The potential shift to a monolithic design for the M3 Ultra raises questions about how Apple will scale the chip's performance without the UltraFusion interconnect. Competing solutions, such as NVIDIA's Blackwell GPU, use a high-bandwidth C2C interface to connect two 104 billion transistor chips, achieving a bandwidth of 10 TB/s. In comparison, the M2 Ultra's UltraFusion interconnect provided a bandwidth of 2.5 TB/s.

Intel Core Ultra "Lunar Lake-MX" will be the company's bulwark against Apple's M-series Pro and Max chips, designed to power the next crop of performance ultraportables. The MX codename extension denotes MoP (memory-on-package), which sees stacked LPDDR5X memory chips share the package's fiberglass substrate with the chip, to conserve PCB footprint, and give Intel greater control over the right kind of memory speed, timings, and power-management features suited to its microarchitecture. This is essentially what Apple does with its M-series SoCs powering its MacBooks and iPad Pros. Igor's Lab scored the motherlode on the way Intel has restructured the various components across its chiplets, and the various I/O wired to the package.

When compared to "Meteor Lake," the "Lunar Lake" microarchitecture sees a small amount of "re-aggregation" of the various logic-heavy components of the processor. On "Meteor Lake," the CPU cores and the iGPU sat on separate tiles—Compute tile and Graphics tile, respectively, with a large SoC tile sitting between them, and a smaller I/O tile that serves as an extension of the SoC tile. All four tiles sat on top of a Foveros base tile, which is essentially an interposer—a silicon die that facilitates high-density microscopic wiring between the various tiles that are placed on top of it. With "Lunar Lake," there are only two tiles—the Compute tile, and the SoC tile.

Intel CEO Pat Gelsinger engaged with press/media representatives following the conclusion of his IFS Direct Connect 2024 keynote speech—when asked about Team Blue's ongoing relationship with TSMC, he confirmed that their manufacturing agreement has advanced from "5 nm to 3 nm." According to a China Times news article: "Gelsinger also confirmed the expansion of orders to TSMC, confirming that TSMC will hold orders for Intel's Arrow and Lunar Lake CPU, GPU, and NPU chips this year, and will produce them using the N3B process, officially ushering in the Intel notebook platform that the outside world has been waiting for many years." Past leaks have indicated that Intel's Arrow Lake processor family will have CPU tiles based on their in-house 20A process, while TSMC takes care of the GPU tile aspect with their 3 nm N3 process node.

That generation is expected to launch later this year—the now "officially confirmed" upgrade to 3 nm should produce pleasing performance and efficiency improvements. The current crop of Core Ultra "Meteor Lake" mobile processors has struggled with the latter, especially when compared to rivals. Lunar Lake is marked down for a 2025 launch window, so some aspects of its internal workings remain a mystery—Gelsinger has confirmed that TSMC's N3B is in the picture, but no official source has disclosed their in-house manufacturing choice(s) for LNL chips. Wccftech believes that Lunar Lake will: "utilize the same P-Core (Lion Cove) and brand-new E-Core (Skymont) core architecture which are expected to be fabricated on the 20A node. But that might also be limited to the CPU tile. The GPU tile will be a significant upgrade over the Meteor Lake and Arrow Lake CPUs since Lunar Lake ditches Alchemist and goes for the next-gen graphics architecture codenamed "Battlemage" (AKA Xe2-LPG)." Late January whispers pointed to Intel and TSMC partnering up on a 2 nanometer process for the "Nova Lake" processor generation—perhaps a very distant prospect (2026).

When TSMC introduced its N3 lineup of nodes, the company only talked about the logic scaling of the two new semiconductor manufacturing steps. However, it turns out that there was a reason for it, as WikiChip confirms that the SRAM bit cells of N3 nodes are almost identical to the SRAM bit cells of N5 nodes. At TSMC 2023 Technology Symposium, TSMC presented additional details about its N3 node lineup, including logic and SRAM density. For starters, the N3 node is TSMC's "3 nm" node family that has two products: a Base N3 node (N3B) and an Enhanced N3 node (N3E). The base N3B uses a new (for TSMC) self-aligned contact (SAC) scheme that Intel introduced back in 2011 with a 22 nm node, which improves the node's yield.

Regardless of N3's logic density improvements compared to the "last-generation" N5, the SRAM density is almost identical. Initially, TSMC claimed N3B SRAM density was 1.2x over the N5 process. However, recent information shows that the actual SRAM density is merely a 5% difference. With SRAM taking a large portion of the transistor and area budget of a processor, N3B's soaring manufacturing costs are harder to justify when there is almost no area improvement. For some time, SRAM scaling wasn't following logic scaling; however, the two have now completely decoupled.

Conflicting reports are flying around about Apple's next generation MacBook Air lineup, mostly surrounding suggestions of a firm release date or debut reveal at WWDC 2023. 9to5Mac claims that its insider sources have pointed to a new range of M3 chipset powered MacBook Air extra thin laptops offered up in two different screen sizes: 13-inch and 15-inch. An insider claimed last month that Apple's upcoming laptop lineup was in an advanced stage of production, and was far along enough to warrant an "imminent" launch window. A Taiwanese publication has presented new evidence this week, and it posits that Apple could drop M3 chipset-based laptops from announcement presentations organized for this year's Worldwide Developers Conference, which is set to take place from June 5 to 9.

According to the financial section of Taiwan's UDN news site, Apple's key decision makers could be in favor of fielding laptops based on its current generation M2 SoC, instead of an entry-level M3-based range, due to delays and changes in priority for the N3B node at TSMC foundries. This is seen as an odd move given reports from earlier this month of Apple requesting a reduction in factory output for its M2 chips, following a slump in demand. Apple could be changing its strategy with regards to the alleged surplus of M2 silicon - the article theorizes that the company will spend more time fitting the older generation chipsets into a new range of laptops and desktop computers. An M3-based product line could be delayed into late 2023, and it is alleged that TSMC has been instructed to concentrate mostly on manufacturing Apple's Bionix A17 mobile chipset via the cutting edge 3 nm FinFet technology process (N3B) - earmarked to debut on the iPhone 15 Pro in autumn 2023.