PCI-SIG has released a small update on its upcoming PCIe 8.0 standard, with the draft milestone reaching version 0.5. Perhaps the most intriguing aspect of this draft update is not the performance itself, but the exploration of a new connector technology to support this high-bandwidth protocol. Last year, we learned that PCI-SIG plans to implement a 256.0 GT/s raw bit rate and 1 TB/s of bidirectional bandwidth in the x16 lane configuration. We had assumed that the protocol would continue using the familiar connector technology seen in previous PCIe updates. However, it turns out that the current connector might be a limiting factor, prompting the search for a replacement for the traditional PCIe electrical connection.

The traditional PCIe connector is a copper-based link with up to 16 lanes connecting graphics cards to a slot. In a full x16 lane configuration, the PCIe generation supported by the motherboard provides the best performance, offering the maximum bandwidth the platform can deliver. However, with a 256 GT/s raw bit rate, the connector provides about 1 TB/s of bidirectional bandwidth, which is eight times faster than the current PCIe 5.0 platform used with modern GPUs and CPUs. This indicates that the current physical layer facilitating communication between a GPU and a motherboard is nearing saturation with the advent of PCIe 8.0, necessitating the consideration of an alternative connection method.

PCI-SIG has announced a clear step forward for peripheral connectivity: PCIe 8.0 is being developed to run at 256 GT/s, which translates to about 512 GB/s in each direction and roughly 1 TB/s of simultaneous bidirectional bandwidth in a full x16 slot. Version 0.3 of the PCIe 8.0 specification has been released to member companies for review, marking the first formal draft from the working group. This draft is an early milestone on a multi-year path toward a final 1.0 release, and member feedback will shape further drafts as the consortium works to complete the standard by the targeted timeframe in 2028.

The draft reiterates several engineering priorities beyond raw speed. PCIe 8.0 will continue to use PAM4 signaling while doubling the bit rate over PCIe 7.0 and quadrupling it over PCIe 6.0, with a strong emphasis on keeping compatibility with past generations. Power efficiency and protocol optimizations for even higher rates are under active consideration, and the working group is testing new connector approaches. Optical links remain a topic of interest because they could extend reach and reduce energy use, but cost and interoperability questions will need to be resolved before they become mainstream in the PCIe ecosystem. Vendors and designers are already reviewing the draft as they plan silicon, switch, and system roadmaps that will leverage the next generation of bandwidth, particularly in high-performance computing and AI.

PCI-SIG today announced the PCI Express (PCIe) 8.0 specification will double the data of the PCIe 7.0 specification to 256.0 GT/s and is planned for release to members by 2028. "Following this year's release of the PCIe 7.0 specification, PCI-SIG is excited to announce that the PCIe 8.0 specification will double the data rate to 256 GT/s, maintaining our tradition of doubling bandwidth every three years to support next-generation applications," said Al Yanes, PCI-SIG President and Chairperson. "With the increasing data throughput required in AI and other applications, there remains a strong demand for high performance. PCIe technology will continue to deliver a cost-effective, high-bandwidth, and low-latency I/O interconnect to meet industry needs."