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Intel "Sapphire Rapids" Brings PCIe Gen 5 and DDR5 to the Data-Center

As if the mother of all ironies, prior to its effective death-sentence dealt by the U.S. Department of Commerce, Huawei's server business developed an ambitious product roadmap for its Fusion Server family, aligning with Intel's enterprise processor roadmap. It describes in great detail the key features of these processors, such as core-counts, platform, and I/O. The "Sapphire Rapids" processor will introduce the biggest I/O advancements in close to a decade, when it releases sometime in 2021.

With an unannounced CPU core-count, the "Sapphire Rapids-SP" processor will introduce DDR5 memory support to the data-center, which aims to double bandwidth and memory capacity over the DDR4 generation. The processor features an 8-channel (512-bit wide) DDR5 memory interface. The second major I/O introduction is PCI-Express gen 5.0, which not only doubles bandwidth over gen 4.0 to 32 Gbps per lane, but also comes with a constellation of data-center-relevant features that Intel is pushing out in advance as part of the CXL Interconnect. CXL and PCIe gen 5 are practically identical.

Intel "Sapphire Rapids" Micro-architecture Succeeds "Tiger Lake"

Intel revealed the very first hint at its post-"Ice Lake"/"Tiger Lake" processor lineup, which will likely be built on the company's 7 nanometer silicon fab process. Its 12th generation Core processor will be built on the new "Sapphire Rapids" silicon, which will be a major micro-architecture change, and could put 8-core into more hands. The processor, along with its companion chipset, will make up the "Tinsley" platform, which is expected to hit the market in 2020.

Following its 8th generation Core "Coffee Lake" lineup, Intel could built 2-3 micro-architectures on its new 10 nm process, namely "Cannon Lake," "Ice Lake," and "Tiger Lake," which could be released over the next three years. "Sapphire Rapids" could be launched on the process that succeeds 10 nm, likely 7 nm, with a launch timeline likely around 2020.
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