Sunday, November 16th 2025

Intel "Granite Rapids-WS" Workstation Xeon SKUs Appear With Up to 336 MB of Cache

Intel is gearing up for a return to the high-end desktop (HEDT) workstation market with the launch of the "Granite Rapids-WS" Xeon processors. A well-known hardware leaker, @momomo_us, has provided a list of potential SKUs, detailing their L3 cache capacities and clock speeds. At the top of this preliminary list is a SKU labeled as the "698X," featuring 336 MB of L3 cache and a clock speed of 2.0 GHz across all cores. The lower clock speed combined with naming conventions suggesting it's a top end SKU tier suggests this should be a higher-core SKU, though this is yet to be confirmed. The Granite Rapids-WS design is based on Intel's XCC server compute dies, incorporating two compute tiles that deliver up to 86 cores with two I/O tiles for connectivity, such as PCIe and memory controllers. To exceed 86 cores, Intel would likely need to adopt the larger UCC die and a bigger package.

The specifics of memory support for the workstation SKU are still uncertain. However, the server XCC family supports DDR5-6400 and can achieve higher effective speeds with MR-DIMMs. For workstations, Intel is likely to opt for an eight-channel memory configuration to balance capacity and board complexity, although a 12-channel memory setup is also possible. The Granite Rapids-WS processors are derived from Intel's server XCC dies, allowing for a quicker path to higher core counts in workstations. These "Granite Rapids" server dies are modified with a new socket and package to suit the specific needs of workstations. Intel manufactures the I/O die for Granite Rapids on the Intel 7 node, while the compute tiles are produced using Intel 3.
Here are the SKUs listed:
698X: 2.00 GHz, 336 MB
696X: 2.40 GHz, 336 MB
678X: 2.40 GHz, 192 MB
676X: 2.80 GHz, 144 MB
674X: 3.00 GHz, 144 MB
658X: 3.00 GHz, 144 MB
656: 2.90 GHz, 72 MB
654: 3.10 GHz, 72 MB
638: 3.20 GHz, 72 MB
636: 3.50 GHz, 48 MB
634: 2.70 GHz, 48 MB
Source: @momomo_us
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7 Comments on Intel "Granite Rapids-WS" Workstation Xeon SKUs Appear With Up to 336 MB of Cache

#1
framebuffer
wonder if you can install an OS in L3 🤔
Posted on Reply
#2
Onasi
framebufferwonder if you can install an OS in L3 🤔
Not really, no. Best you can do is use CAR (cache as ram) for Coreboot. Even if you were able to, it wouldn’t be useful since you wouldn’t be able to display anything - DMA is required for the GPU and even if said GPU is on the same chip it cannot access CPU cache, period.
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#3
Wirko
The Granite Rapids-WS design is based on Intel's XCC server compute dies, incorporating two compute tiles that deliver up to 86 cores with two I/O tiles for connectivity, such as PCIe and memory controllers. To exceed 86 cores, Intel would likely need to adopt the larger UCC die and a bigger package.
Can't they glue together three XCC dies and two I/O dies, just like they do to make server Xeons? Exactly the ones in the photo? If they can't because the new WS socket isn't huge enough then UCC won't help either, because the surface area simply won't be sufficient for all the cores and I/O.
Posted on Reply
#4
twin_savage
two I/O tiles for connectivity, such as PCIe and memory controllers.
Intel did not follow AMD's misguided path of putting the memory controllers on a completely separate die. The GNR memory controllers are directly on the compute tiles to keep NUMA domain performance tight like a monolithic chip.
Posted on Reply
#5
vmetodiev
OnasiNot really, no. Best you can do is use CAR (cache as ram) for Coreboot. Even if you were able to, it wouldn’t be useful since you wouldn’t be able to display anything - DMA is required for the GPU and even if said GPU is on the same chip it cannot access CPU cache, period.
There is a way for a peripheral to make a DMA transfer directly into the cache. Have a look at this: www.intel.com/content/www/us/en/io/data-direct-i-o-technology.html

AMD have been working on their own implementation, called Smart Data Cache Injection (SDCI), which also allows injection not only to the last-level (L3) cache, but to the L2 as well.
www.amd.com/content/dam/amd/en/documents/processor-tech-docs/white-papers/x4-sdci-whitepaper.pdf
Posted on Reply
#6
Wirko
vmetodievThere is a way for a peripheral to make a DMA transfer directly into the cache. Have a look at this: www.intel.com/content/www/us/en/io/data-direct-i-o-technology.html

AMD have been working on their own implementation, called Smart Data Cache Injection (SDCI), which also allows injection not only to the last-level (L3) cache, but to the L2 as well.
www.amd.com/content/dam/amd/en/documents/processor-tech-docs/white-papers/x4-sdci-whitepaper.pdf
Very interesting! However, every cache line maps to a location in system memory, so it would probably be impossible to make a processor operational with less RAM than cache. (Also it's a bit hard to find 128-megabyte DDR5 sticks.)
Posted on Reply
#7
vmetodiev
WirkoVery interesting! However, every cache line maps to a location in system memory, so it would probably be impossible to make a processor operational with less RAM than cache. (Also it's a bit hard to find 128-megabyte DDR5 sticks.)
I guess they may be using the address space in a way that there is a region reserved only for cache mapping (and the IOMMU being able to present it to the peripherals for DMA). By doing so, the DDR controller will not need to "synch" by executing writes to the RAM. The 64-bit space is still much larger to go beyond the maximum cumulative RAM that can be installed on a system.
(At least that is how I will approach the topic if I worked as a CPU design engineer at AMD or Intel) 🤪

Still, your point is very valid as well - AFAIK, the approach that you describe is the one used by ARM - the so called "cache stashing". And if my theory from the above lines is valid, that gives the x64 CPUs significant advantage over Aarch64.
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Nov 11th, 2026 03:18 CST change timezone

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