Tuesday, December 19th 2017
Intel Unveils Industry's First FPGA Integrated with HBM - Built for Acceleration
Intel today announced the availability of the Intel Stratix 10 MX FPGA, the industry's first field programmable gate array (FPGA) with integrated High Bandwidth Memory DRAM (HBM2). By integrating the FPGA and the HBM2, Intel Stratix 10 MX FPGAs offer up to 10 times the memory bandwidth when compared with standalone DDR memory solutions1. These bandwidth capabilities make Intel Stratix 10 MX FPGAs the essential multi-function accelerators for high-performance computing (HPC), data centers, network functions virtualization (NFV), and broadcast applications that require hardware accelerators to speed-up mass data movements and stream data pipeline frameworks.
In HPC environments, the ability to compress and decompress data before or after mass data movements is paramount. HBM2-based FPGAs can compress and accelerate larger data movements compared with stand-alone FPGAs. With High Performance Data Analytics (HPDA) environments, streaming data pipeline frameworks like Apache Kafka and Apache Spark Streaming require real-time hardware acceleration. Intel Stratix 10 MX FPGAs can simultaneously read/write data and encrypt/decrypt data in real-time without burdening the host CPU resources.
"To efficiently accelerate these workloads, memory bandwidth needs to keep pace with the explosion in data" said Reynette Au, vice president of marketing, Intel Programmable Solutions Group. "We designed the Intel Stratix 10 MX family to provide a new class of FPGA-based multi-function data accelerators for HPC and HPDA markets."
The Intel Stratix 10 MX FPGA family provides a maximum memory bandwidth of 512 gigabytes per second with the integrated HBM2. HBM2 vertically stacks DRAM layers using silicon via (TSV) technology. These DRAM layers sit on a base layer that connects to the FPGA using high density micro bumps. The Intel Stratix 10 MX FPGA family utilizes Intel's Embedded Multi-Die Interconnect Bridge (EMIB) that speeds communication between FPGA fabric and the DRAM. EMIB works to efficiently integrate HBM2 with a high-performance monolithic FPGA fabric, solving the memory bandwidth bottleneck in a power-efficient manner.
Intel is shipping several Intel Stratix 10 FPGA family variants, including the Intel Stratix 10 GX FPGAs (with 28G transceivers) and the Intel Stratix 10 SX FPGAs (with embedded quad-core ARM processor). The Intel Stratix 10 FPGA family utilizes Intel's 14 nm FinFET manufacturing process and incorporates state-of-the-art packaging technology, including EMIB.
Source:
Intel Newsroom
In HPC environments, the ability to compress and decompress data before or after mass data movements is paramount. HBM2-based FPGAs can compress and accelerate larger data movements compared with stand-alone FPGAs. With High Performance Data Analytics (HPDA) environments, streaming data pipeline frameworks like Apache Kafka and Apache Spark Streaming require real-time hardware acceleration. Intel Stratix 10 MX FPGAs can simultaneously read/write data and encrypt/decrypt data in real-time without burdening the host CPU resources.
The Intel Stratix 10 MX FPGA family provides a maximum memory bandwidth of 512 gigabytes per second with the integrated HBM2. HBM2 vertically stacks DRAM layers using silicon via (TSV) technology. These DRAM layers sit on a base layer that connects to the FPGA using high density micro bumps. The Intel Stratix 10 MX FPGA family utilizes Intel's Embedded Multi-Die Interconnect Bridge (EMIB) that speeds communication between FPGA fabric and the DRAM. EMIB works to efficiently integrate HBM2 with a high-performance monolithic FPGA fabric, solving the memory bandwidth bottleneck in a power-efficient manner.
Intel is shipping several Intel Stratix 10 FPGA family variants, including the Intel Stratix 10 GX FPGAs (with 28G transceivers) and the Intel Stratix 10 SX FPGAs (with embedded quad-core ARM processor). The Intel Stratix 10 FPGA family utilizes Intel's 14 nm FinFET manufacturing process and incorporates state-of-the-art packaging technology, including EMIB.
15 Comments on Intel Unveils Industry's First FPGA Integrated with HBM - Built for Acceleration
I find it pretty funny that AMD created so much hype around HBM2, like if it was their in-house tech. And few months (soon: years...) later it looks like Intel and NVIDIA went all HBM2 in their enterprise/premium products, while AMD is designing a DDR-based Vega APU and making excuses for low GPU supply. :-/
I do hope they're at least getting something for the license. I'd love some HBM3.
AMD went with SK Hynix, I think most of these products have Samsung's HBM & no HBM2 wasn't (just) from the House of Red.
AMD part was the substrate, and some contract that it would get the first supply of HBM memory modules for the Fury X for example. But as for HBM2 AMD needs to be in line simular as Nvidia, Intel and all the other partners wanting a piece of that silicon.
From the official launch slides:
But I think this is even better:
From the ex big man Raja himself: "there are over 200 features in Vega, but if I had to pick one, that in the long run is going to have the most impact, it's the high bandwidth cache"
What followed the AMD "leaks" and launch info, were thousands of Vega zealots running around forums and saying that HBM2 is fundamental for Vega. It's slightly improbable that they all invented the same story themselves, right? :-)Yet everyone else just uses it without much storytelling. In the green camp it's just some new, faster memory.
In the red camp it's a legendary piece of tech, a historical achievement of humanity. Suddenly everyone is talking about HBM2.
But more importantly: it's clear that other companies don't find it that hard to obtain the amount of HBM2 they need. AMD does, supposedly.
I'm only pointing that AMD made a huge fuzz around it, suggesting not just revolutionary tech (which hardly anyone cares about) but also revolutionary performance (what is important).
And we ended up with a GPU that struggles to compete with more traditional, refined products. So they've diverted consumers' attention from what's actually important and created another fanboy topic: HBM2 changing the world.
But because AMD failed to deliver, who will actually benefit from HBM2 are typical Intel and NVIDIA customers - people that really don't care what's inside and how it is called. They want things to work well and they'll get just that.
The problem with traditional (and shrinking) AMD client base is that they don't concentrate on important, high-level stuff: like performance, power consumption, portability or flexibility. They concentrate on mostly pointless, geeky-sounding tech details: HBM, IPC, Infinity Matrix and so on.
It reminds me a situation that you often see in a PC store. A mid-50s woman comes to buy a laptop and she knows exactly what she wants: use MS Office, browse the web, watch movies and so on. The seller is around 20 and he took this job, because he loves tech, but - sadly - he doesn't really know much about selling stuff, nor does he understand that woman's needs. So what he will actually say is: "take this one, because it has more cores and an SSD". :-)
Watch the video above. Look how much time Raja (the man in charge!) spends on really just storytelling about how awesome the tech is. And it's an official presentation material for clients, not some internal learning stuff.
Intel will NEVER let him create a video like this one. This would just offend their clients - even gamers (let alone pros and typical home consumers).
The thing with HBM, even from the start, is that the ram modules are physically closer to the processor they're serving. In the case of Radeon GPU's and NVidia's new hotness, the distance to the GPU is measured in mm instead of cm. Time of electrons traveling through a circuit pathway in measured in billionths of a second. That may seem increasingly small but when it takes dozens, if not hundreds, of clock cycles to travel that distance, any chance to reduce that distance of travel should be taken advantage of. In the case of the FPGA Intel is making, it means that performance will not be hampered by latentcies of distance based ram access time and the FGPA can be programed to simulate, not emulate, nearly any type of technology it has the capacity to store the logic gates for.
Could you please give me a rough estimate: what percentage of PC users - in your opinion - should care about the distance between processor and memory? :-)
And once again, yes: it has a huge impact on performance.
HBCC means we can monitor system memory by the video card which is Project Labaree/Xeon Phi datacenter competitor.
And my gaming pc with a overclocked waterblocked vega 64 doing 43mh/s.
Everyone notes hashrate as the measure ,it isn't.
It's share submission and that's where the above show an interesting aside of hbm memorys low latency the miners submitted 7349 shares ,the vega on it's own 4700, and you get Paid for shares not hashes.(4 days ish mining eth only on nanopools)
This is a mirage , what's behind, is a hot non existent chip according to some ie chalie D.
I'm looking at this from the point of view that these would be absolutely loved by devs ,if out designs would be out, shot id start designing a mining algo circuit for one myself right now if i didnt know several companies are likely on it.