Tuesday, October 10th 2017

TSMC 7 nm Second-Generation EUV Chips Taped Out, 5 nm Risk Production in April 2019

TSMC, the world's biggest contract semiconductor manufacturer, who is at the forefront of 7 nanometer production has just announced that they are making good progress with their second generation of 7 nm technology "N7+", using EUV (Extreme Ultraviolet Lithography). A first design for N7+ from an unnamed customer has been taped out. The company's first-gen 7 nm production is running well already, with final products, like Apple iPhone already in the hands of customers.

While not fully EUV yet, the N7+ process will see limited EUV usage, for up to four non-critical layers, which gives the company an opportunity to figure out how to make best use of the new technology, how to ramp up for mass production and how to fix the little quirks that show up as soon as you move from the lab to the factory.
The new technology is expected to bring 6-12% lower power and 20% better density, which could be especially important for power and heat constrained designs. It will also be a good marketing vehicle for many of TSMC's customers who are expected to release new designs every year. With the N7+ process, TSMC is targeting the automotive sector, too, where releases happen more slowly, which suggests that this process will be available for a long time.

Moving beyond 7 nanometers, TSMC's target is 5 nm, internally called "N5". This process will use EUV for up to 14 layers and is expected to be ready for risk production in April 2019. According to TSMC, many of their IP blocks are ready for N5, with the exception of PCIe Gen 4 and USB 3.1. We have all been waiting for PCIe Gen 4 on new GPUs and it looks like we'll have to wait even longer for this new version to become available. Compared to the N7 designs, which have initial costs in the $150 million range, the cost for N5 is expected to increase even further, up to $200 to $250 million. Source: EETAsia
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22 Comments on TSMC 7 nm Second-Generation EUV Chips Taped Out, 5 nm Risk Production in April 2019

#1
londiste
The company's first-gen 7 nm production is running well already, with final products, like Apple iPhone and NVIDIA GeForce RTX already in the hands of customers.
Wait, what?
Posted on Reply
#2
T1beriu
5 nm RISK Production in April 2019

It's not HVM (High Volume Manufacturing), it's risk production where each IC manufacturer makes a few hundred test wafers to test the final silicon in their labs and to sample its partners that integrate it in their products.

We won't see 5nm HVM until Q2 2020 and actual silicon in products in Q3/Q4 2020 (probably, as it happened for the last 2-3 years, in the 2020 iPhone).

Very misleading this title and information is.
Posted on Reply
#3
XiGMAKiD
londiste said:
Wait, what?
My reaction exactly
Posted on Reply
#4
Gungar
londiste said:
Wait, what?
I guess Wizzard hasn't got the morning coffee yet.
Posted on Reply
#5
Nkd
londiste said:
Wait, what?
Yea this article seems like rushed. LOL! The 7nm RTX part had me going. The way it was worded was that people already have them lol. Like APPLE 7nm which is in Iphone xs and xs max. So call me confused and other 5nm info was all over the place too.
Posted on Reply
#6
techy1
Wizz - please clarify or fix that 7nm Nvidia RTX - or some tech reporters will start to multiplicate and runaway with this info.
maybe I can fix it for you: "Nvida RTX 5nm in April 2019, Confirmed!" :D
Posted on Reply
#7
tmtisfree
The new technology is expected to bring 6-12% lower power and 20% better density
Compared to what?
Posted on Reply
#8
Frick
Fishfaced Nincompoop
tmtisfree said:
Compared to what?
12nm I assume.

And 5nm mass production in April 2019 is not feasible.
Posted on Reply
#9
ppn
tmtisfree said:
Compared to what?
7+ nm 20% better density than 7 ~~120 Mtr/mm2
7 nm features 1.6X logic density than 10 ~~100 Mtr/mm2
10 nm 2X logic density than 12/16nm ~~60 Mtr/mm2

We are at 1.2X1.6X2 ~ 4X better logic density at this point in time, and still not getting it in real GPU products.

All we have for now is 12/14/16 nm with ~~30 Mtr/mm2.

yeah this means RTX 2080Ti 754mm2 the size of GTX 1060 with 200mm2 if tape out next year.
Posted on Reply
#10
W1zzard
londiste said:
Wait, what?
Yeah I failed, wtf was I thinking

Gungar said:
I guess Wizzard hasn't got the morning coffee yet.
no breakfast yet either and i've been up for 5 hours already
Posted on Reply
#11
atomicus
N7+ is AMD's 2080Ti killer!! :D
Posted on Reply
#12
T1beriu
W1zzard said:
Yeah I failed, wtf was I thinking
What about what I said about 5nm high volume production? The article is still misleading!!!
TSMC's target is 5 nm, internally called "N5". This process will use EUV for up to 14 layers and is expected to be ready for mass production in April 2019.
Here's a quote from the source:
SAN JOSE, Calif. — TSMC taped out its first chip in a process making limited use of extreme ultraviolet lithography and will start risk production in April on a 5-nm node with full EUV.
Risk production starts a year before mass production. Dude, you should now this stuff by now because you're many years in the game. Step it up!
Posted on Reply
#13
W1zzard
T1beriu said:
What about what I said about 5nm high volume production? The article is still misleading!!!


Here's a quote from the source:



Risk production starts a year before mass production. Dude, you should now this stuff by now because you're many years in the game. Step it up!
Fixed again
Posted on Reply
#14
ppn
atomicus said:
N7+ is AMD's 2080Ti killer!! :D
No, AMD is using 60 MTr/mm2 2x density of 14nm, that is not 7nm. Unless it is based on 10nm.
Posted on Reply
#15
atomicus
ppn said:
No, AMD is using 60 MTr/mm2 2x density of 14nm, that is not 7nm. Unless it is based on 10nm.
I was joking lol.
Posted on Reply
#16
Indurain
WTF is RISK? Did you mean RISC? ;):eek:

Hmm, I see that the original source says 'risk' which is wrong, unless they are trying to say, very poorly I might add, that production of 5 nm is AT RISK, which of course they are not saying.
Posted on Reply
#17
efikkan
EUV have been the elephant in the room for a long time. Both TSMC 7nm and Intel 10nm needs EUV for high volume cost effective production. A slow adoption of EUV makes sense, but this doesn't seem like it's going to speed up the process a lot, since the bottleneck is the triple/quadruple patterning on DUV.

ppn said:
7+ nm 20% better density than 7 ~~120 Mtr/mm2
7 nm features 1.6X logic density than 10 ~~100 Mtr/mm2
10 nm 2X logic density than 12/16nm ~~60 Mtr/mm2

We are at 1.2X1.6X2 ~ 4X better logic density at this point in time, and still not getting it in real GPU products.
That's not how it works.
TSMC and GloFo 16/14/12nm => TSMC 7nm allows up to 3-4× increased density, but it also limited by W/mm², and the clocks they want to run the chip on.
Posted on Reply
#18
WikiFM
Until we know the metrics of TSMC's 7+ nm we are not sure if it is comparable or better than Intel's 10 nm or still behind, like 7 nm.
Posted on Reply
#19
londiste
efikkan said:
EUV have been the elephant in the room for a long time. Both TSMC 7nm and Intel 10nm needs EUV for high volume cost effective production. A slow adoption of EUV makes sense, but this doesn't seem like it's going to speed up the process a lot, since the bottleneck is the triple/quadruple patterning on DUV.
As far as I understand, EUV will give the same results without quadruple patterning. This being the main factor for speed increase both for production as well as easier patterning.
EUV has around 15 times smaller wavelength compared to DUV which allows for smaller features. The actual devices do 30-50% smaller resolution compared to DUV devices.
There are downsides and challenges both technical as well as getting enough EUV devices to run volume production.

WikiFM said:
Until we know the metrics of TSMC's 7+ nm we are not sure if it is comparable or better than Intel's 10 nm or still behind, like 7 nm.
From what TSMC has disclosed, Intel's 10nm should be in between TSMC's N7 and N7+ in most metrics.
Posted on Reply
#20
Batya
Indurain said:
WTF is RISK? Did you mean RISC? ;):eek:

Hmm, I see that the original source says 'risk' which is wrong, unless they are trying to say, very poorly I might add, that production of 5 nm is AT RISK, which of course they are not saying.
Remember that Google is your friend ;)
Posted on Reply
#21
efikkan
londiste said:
As far as I understand, EUV will give the same results without quadruple patterning. This being the main factor for speed increase both for production as well as easier patterning(…).
Yes, but as the article says, they will limit its use to non-critical layers. So in other words, the "hard stuff" will still be done on DUV for the time being. The production costs will remain high.

It will be interesting to see when EUV are fully adapted, maybe we will even move into 5nm territory by that time.
Posted on Reply
#22
londiste
efikkan said:
It will be interesting to see when EUV are fully adapted, maybe we will even move into 5nm territory by that time.
Samsung is said to embrace EUV for their 7nm process. To what degree exactly I don't think anyone publicly knows. This is also what is driving the delay for their 7nm.
Posted on Reply
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