SK hynix reported its latest Q3 2026 quarterly results with a record $78.129 billion in net revenue. However, the company also shared a market outlook, highlighting its long-term supply agreements and plans for expansion with new fab capacity and facilities under construction. For the consumer market, the outlook is grim as SK hynix expects memory demand to continue outpacing supply through 2030. The main supply constraint is the complexity of leading-edge semiconductor nodes and the lengthy lead times for fab construction, which take years to translate into regular mass production volumes.

Despite sustained demand, pricing is also on an upward trajectory, with the average selling price of memory modules in Q3 increasing by over 20% compared to Q2. This is concerning, as it suggests that the prices of consumer electronics devices might jump by more than 20% once memory inventory is depleted. Although SK hynix expects a decrease in PC and smartphone shipments, this will be offset by a strong rollout of AI data centers. About 14 major customers, including most hyperscalers, have signed 5-year long-term agreements, which will account for over 50% of total capacity sold for 2027 and 2028.

Chinese startup Langdao Silex has demonstrated the development of the first homegrown extreme ultraviolet lithography (EUV) laser source, gradually paving the way for China's complete supply chain independence. The system, named FlintNano LPP-OXXO, reportedly delivers over 15 W of EUV output and uses components that are approximately 90% domestically sourced or developed. It relies on laser-produced plasma (LPP), a technique using high-powered lasers to generate plasma and produce the EUV radiation required for advanced chip manufacturing, similar to the process used by ASML. According to specifications published by Langdao Silex, the FlintNano system employs a 1,000 W driving laser operating at repetition rates between 1 and 20 kHz. Its conversion efficiency exceeds 2%, and the company claims the equipment can operate continuously for more than 100 hours. The prototype is reportedly suitable for wafer exposure testing, although further finetuning is still necessary.

Readers might recall that EUV lithography tools are banned from being sold in China, as the United States government previously pressured the Dutch government to halt sales of these advanced tools. In fact, ASML has never shipped a single EUV scanner to China, as the Dutch government, under pressure from the United States, blocked exports in 2019. Not a single system has been deployed, but ASML continues to ship DUV systems to Chinese customers. More importantly, developing a light source is only one part of building a complete EUV scanner. Such systems also require extremely precise reflective optics, sophisticated wafer positioning mechanisms, and complex integration across numerous subsystems.

ASML today reported its Q3 2026 financial results, with gross revenue totaling €11.7 billion, a gross margin of 57.5%, and a net income of €5.0 billion. ASML also provided updates on its system sales by region, revealing that shipments to China have become one of its strongest areas for system sales. Chinese semiconductor manufacturers are rushing to stockpile more tools. In the previous Q2, net system sales to China accounted for 14% of ASML's sales. In the latest Q3, this figure has grown to 23%, nearly a quarter of all ASML's system sales. In Q3, Taiwan remains the largest buyer of ASML equipment at 32%, followed by South Korea at 31%. China takes third place with 23%, and the United States follows with 13%.

The strong demand from China is reportedly due to Chinese memory and storage makers stockpiling enough lithography tools from ASML to support their expansion plans for the next three years, even if they are cut off from the supply chain. According to earlier reports, memory maker CXMT and storage giant YMTC have secured sufficient DUV lithography tools from ASML to support their growth plans for the next three years, despite increasing tensions and potential bans on exporting these older DUV tools to China. The United States government is reportedly pressuring the Dutch government to completely halt tool exports to China.

Samsung Foundry may be on the verge of securing a significant deal with AI lab Anthropic to manufacture AI accelerators. According to the latest report, Anthropic is developing its custom AI accelerator on Samsung's SF2 2 nm node, which will initially be produced in a lower volume of around 200,000 chips. The design and implementation of this ASIC are being handled by Broadcom, targeting around 4,000 TOPS of INT8 compute, with a TDP of 1,300 W per chip. This will be supported by either 192 GB of HBM3E or even 288 GB of HBM3E, if the design allows. The current production volume is low, as ASIC projects are typically counted in millions of chips. However, Anthropic is likely evaluating the project's viability, which requires a complete custom infrastructure with networking, rack design, power supply, cooling, and many other factors.

The current Samsung SF2 node is built using Low-NA EUV lithography and is manufactured in South Korea, with a new facility soon to be established in Taylor, Texas. For packaging these chips and integrating them with HBM, Samsung is likely to employ its I-Cube technology, which rivals TSMC's CoWoS and allows for 2.5D packaging. Combined with the 2 nm dies, Samsung can position itself as a serious manufacturing plant for external customers and slightly close the gap with TSMC and its contract manufacturing business.

Qualcomm announced today that it is officially licensing technology from Chinese technology giant Huawei. In a deal estimated to be worth $6.9 billion upon completion, Qualcomm will license various technologies from Huawei to integrate across its product portfolio. According to official releases, these technologies include computing, AI, networking, and more. Bloomberg reports that the deal also covers Huawei's latest LogicFolding silicon design. This is a significant win for Huawei, whose R&D teams have spent years designing a way to bypass sanctions and overcome manufacturing technology limits. By stacking silicon vertically across two sheets, LogicFolding dramatically reduces the distance between compute elements, increases efficiency, and significantly improves transistor density. The result is a 55% increase in transistor density and a 41% boost in power efficiency.

Update, 06:30 UTC, October 6: Qualcomm issued a statement that dismantles rumors that the company is licensing LogicFolding technology.

QualcommQualcomm and Huawei entered into a multi-year, broad patent license agreement that includes cross-licenses across a range of technology fields. The terms are confidential, but reports characterizing Qualcomm as a net payor on the license agreement are incorrect. In addition, assertions that the agreement is related to LogicFold are not accurate. Separately, Qualcomm has agreed to purchase certain Huawei non-cellular U.S. patents across multiple technology areas.

Chinese semiconductor maker SMIC has increased its market share as the world's third-largest chipmaker. According to the latest report from TrendForce, SMIC now holds 5.4% of the semiconductor manufacturing market share in Q2 this year, a slight increase from 5.1% in Q1. In the three-month period ending in June, SMIC generated about $3 billion in revenue from domestic companies producing homegrown silicon. This marks a significant improvement compared to $2.2 billion in Q2 2025, with a slight increase in market share from that period's 5.1%. This indicates that overall capacity has increased across the supply chain.

SMIC's most advanced manufacturing nodes include the SMIC N+2, a 7 nm-class node used by Huawei to manufacture its Ascend series of AI accelerators and other infrastructure parts, and the SMIC N+3, a 5 nm-class node for its customers. The company uses DUV to print silicon designs but faces significant challenges in achieving its silicon ambitions as it currently has no access to EUV tools, since ASML has restricted exports of its EUV scanners, and it is the only company manufacturing EUV machinery at scale.

Samsung Electronics and ASML today announced an expansion of their long-standing strategic partnership, deepening collaboration on High NA EUV lithography and advanced semiconductor manufacturing technologies that will help drive the next generation of innovation in the AI era.

Building on years of successful cooperation, the companies will work together to accelerate the development and deployment of technologies that support the increasing performance and efficiency requirements of advanced semiconductor manufacturing.

ASML Holding N.V. (Euronext: ASML, Nasdaq: ASML) and Taiwan Semiconductor Manufacturing Company (TWSE: 2330, NYSE: TSM) announced a collaborative initiative to lead the semiconductor industry's transition to a larger-format Extreme Ultraviolet (EUV) lithography photomask.

While High NA EUV will be adopted for production using the current, 6-inch masks, the transition to larger, 12-inch masks is expected to further increase fab productivity, lower chipmaking costs and remove stitching constraints, benefiting the entire semiconductor industry. It will enable advanced chip manufacturers to fully leverage the advantages of High NA EUV, making future generations of leading-edge chips more cost-effective.

Intel has officially processed one million 300 mm silicon wafers using High Numerical Aperture (High NA) Extreme Ultraviolet (EUV) lithography, as confirmed by the company yesterday. Using High-NA in silicon manufacturing presents many challenges due to the additional complexity it introduces, but for Intel, the opposite is true. Initially, Intel installed ASML's TWINSCAN EXE:5000 High-NA EUV systems in 2024 for research and testing of the 14A node. However, since then, Intel has found more useful ways to employ High-NA tools beyond the 14A node, extending their use to the 18A node, which was previously believed to be exclusive to 14A.

For a select subset of "Panther Lake" SKUs, Intel is etching a few layers of silicon using High-NA exposure, instead of solely relying on Low-NA. Furthermore, Intel is offering this High-NA setup to external customers, as it could be beneficial for them as well. In collaboration with ASML, Intel has completed acceptance testing at Intel Foundry for its 14A node to enhance wafer output. This is done using TWINSCAN EXE:5200B, which is ASML's second version of High-NA EUV scanners, following the TWINSCAN EXE:5000 that Intel initially used for its 14A trial runs. Intel previously reported processing over 30,000 wafers in a single quarter, achieving simplified manufacturing by reducing the steps needed for a specific layer from 40 to fewer than 10, resulting in significantly faster cycle times.

SK hynix is shifting much of its capacity to the latest 1c DRAM node, according to recent reports. The South Korean giant is transitioning the bulk of its memory production between nodes, and as DRAM technology advances, the company is moving its production to more advanced 10 nm-class nodes. For SK hynix, the sixth-generation 10 nm class 1c DRAM node accounted for 10% of production in Q1 2026, with an increase to about 13% in Q2. In the current third quarter, the company is expected to manufacture 24% of its DRAM on 1c, while Q4 will see more than a third (34%) produced on that node. By Q1 2027, the 1c node will account for around 35%, making the fifth-generation 10 nm-class 1b node at 33%, officially SK hynix's most dominant node.

As a reminder, DRAM nodes are not the same as conventional logic nodes. DRAM manufacturers use variations of 10 nm and scale them with more EUV layers or advanced features. For SK hynix, the currently dominant 1b node is around 12-13 nm in actual design and involves about 4 layers of EUV patterning, while the most advanced 1c node shrinks to 11-12 nm with 5-6 layers of EUV. SK hynix will use the 1c node to manufacture HBM4E, LPDDR6, and DDR5 memory. For the older 1b node, SK hynix produces DDR5, LPDDR5X, HBM3E, and HBM4.

According to the latest report from ETNews, citing supply chain sources, TSMC is reportedly still holding back from investing in the silicon packaging technology known as hybrid bonding for HBM memory integration. For those unfamiliar, hybrid bonding creates a permanent bond between two silicon chips using embedded metal bumps that are fused together to form a single chip. Multiple dies or entire silicon wafers can be connected by stacking the back ends of two chips together. This technology eliminates traditional chip bumps and directly bonds copper interconnections between the two chips. In modern packaging, chip solder bumps, which stick out before the chip is soldered to the PCB, are roughly 100 micrometers in size, while microbumps are approximately 20 micrometers. Hybrid bonding reduces this size to 1 micrometer. Microbumps are used to interconnect silicon with other chips inside a package, as seen in CoWoS-S and CoWoS-L, where microbumps are prevalent for chip-to-interposer connections.

For TSMC, the future may involve bypassing hybrid bonding technology for packaging HBM memory and investing in microbumps that are 5 micrometers in size. Reportedly, TSMC is preparing its supply chain for 5-micrometer microbumps, which will be even smaller than what is currently available, to enhance performance in packaging. South Korean and Japanese suppliers are reportedly collaborating with TSMC to achieve this, with mass production of 5-micrometer microbumps expected in the second half of 2028. As a reminder, AMD's 3D V-Cache technology uses hybrid bonding to put SRAM on top of logic, but TSMC reportedly plans to keep integration of HBM memory into packaging on microbumps for now.

Rapidus has laid out its advanced packaging roadmap at the 2026 OCP APAC Summit, with eight-reticle-size interposers and 600 x 600 mm panel-level processing as the targets for around 2030. The roadmap was presented by Rapidus Design Solutions CTO Rozalia Beica and shows steps through interposer sizes from four reticles (3,320 mm²) to six (4,980 mm²) and eventually eight (6,640 mm²) by 2030. The 600 x 600 mm panel format is the most important target of that plan as the yield advantage at panel scale is substantial. CTO Beica illustrated the output difference in a simple manner: an eight-reticle interposer yields four units on a standard 300 mm wafer, nine on a 300 x 300 mm panel, 36 on a 510 x 515 mm panel, and 49 on a 600 x 600 mm panel. Taiwanese rival TSMC has its own CoWoS interposer roadmap showing plans aiming for 5.5 reticles in 2026, 9.5 in 2027, and 14 reticles in 2028. However, the two companies are taking different manufacturing approaches. Rapidus is betting on panel-level processing rather than wafer-based scaling.

The 600 mm panel strategy is underway, with Rapidus demonstrating the format and working with Lam Research's Kallisto electroplating system to develop 2.xD packaging with redistribution layers formed on 600 mm glass carriers. We reported in late 2025 that Rapidus produced the first large-format glass interposer prototype and plans to enter mass production in 2028. Last year, Rapidus taped out a 2 nm GAA test chip using ASML EUV tools claiming a transistor density of 237 MTr/mm². Its FY2026 plan brings the Rapidus Chiplet Solutions pilot line into full operation to verify 2.xD and 3D packaging processes.

Lam Research Corp. (NASDAQ: LRCX) today announced that it intends to invest more than $3 billion over the next five years to expand its global research and development (R&D) lab network. The planned multi-site expansion is expected to add infrastructure and capabilities to increase experiment capacity by more than 50%. Lam's R&D approach combines specialized labs worldwide, each purpose-built to accelerate a distinct step of the innovation cycle, with deep customer collaboration that includes locations near customer facilities. Together, Lam's labs operate as an integrated 24/7 network, enabling innovation in parallel and at scale. With this investment, Lam intends to further compress product development cycles for customers, from pathfinding to fab deployment.

"In the AI era, the pace of innovation is relentless, requiring chips with new architectures, different materials, and complex features engineered with nanoscale precision. Our ability to increase velocity throughout the R&D process has become a decisive advantage," said Tim Archer, president and chief executive officer of Lam Research. "We are investing with the intention of staying ahead of what our customers need, further strengthening our global innovation engine to deliver the next generation of semiconductor breakthroughs."

Samsung Foundry has been consistently upgrading its chip-making tools. However, despite the availability of the new generation of EUV lithography, the company has not yet committed to using High-NA EUV lithography tools from ASML. According to ZDNet Korea, this is expected to change with the development of Samsung's 1 nm node, scheduled for 2030. This will be one of the last introductions of High-NA EUV machinery across leading-edge semiconductor node designs. Intel is gradually scaling up its 14A node to risk production with High-NA EUV tools, while TSMC is expected to introduce it in 2029. Samsung being one of the last does not necessarily mean the company is in a rush, as it is currently performing well with the existing Low-NA EUV tools.

For reference, TSMC claims it can maintain a competitive advantage using the existing Low-NA EUV technology for now, scaling nodes down and introducing improvements with each generation. Low-NA tools are also half the price of the premier High-NA EUV systems. The most advanced High-NA EUV machine from ASML costs around $400 million, which is an incredibly expensive piece of machinery, even for a modern semiconductor fab. Hence, TSMC has refrained from using it for now as it can achieve similar advantages with the current Low-NA technology, and Samsung appears to be following this decision.

Nanya Technology Board of Directors announced on August 5 that the company has launched its largest investment program, committing up to NT$346.6 billion (around $10.7 billion) to its Fab5A facility through 2026-2029. The project covers 10 nm-class processes from 1b through 1e nodes and introduces EUV lithography. Nanya has also increased its 2026 capital expenditures budget by 34% to NT$69.7 billion (around $2.16 billion). The extra NT$17.7 billion is going toward advance payments for equipment to keep Fab5A on schedule. The production roadmap has wafer starts being produced in the second half of 2027, reaching 30,000 wafers per month in 2028 and 35,900 in 2029. The maximum planned capacity is around 45,000 wafers monthly. The 1c pilot production has already begun, while the 1d node is under development and expected to enter pilot production soon. Nanya Fab5A investment, when completed, is estimated at roughly $16 billion, deployed in phases based on market demand.

Commercially, Nanya is having a strong run. July revenue hit NT$43.87 billion (around $1.3 billion), up 49.3% month over month and 719.6% year over year, driven by continued DRAM price increases, particularly sharp gains in DDR4 contract prices. Remember that just a year ago DDR4 module prices overtook DDR5 for the first time, with Nanya among the biggest beneficiaries. Its customers include giants like NVIDIA, Google, Microsoft, Intel, AMD, and Qualcomm, with the future looking great for the Taiwanese company. Its long-term agreements reportedly now cover about 50% of production capacity, with short-term contracts gradually converted into long-term agreements.

According to the latest information from the second quarter financial results, ASML is considering raising prices for its Low-NA EUV tools, which is reportedly upsetting its customers. ASML CFO Roger Dassen has noted that the company is looking into price increases for these tools, aligning its pricing strategy with product value. As the company continues to enhance the productivity of its tools, ASML plans to adjust pricing accordingly. The company operates a business unit called Installed Base Management, which focuses on maintaining and improving existing machines. Most of the recent productivity gains have come from ASML's software that operates EUV machines, and the company recently confirmed that:

ASML CFO Roger DassenWhen it comes to Low-NA pricing, of course, you know that we keep on increasing the productivity of the Low-NA tool. Of course, that gives us a pretty strong runway for potential price improvements going forward... Value-based pricing is the concept that we follow within ASML. In the current environment, of course, the value for customers is higher than in other circumstances.

Today, ASML Holding NV (ASML) has published its 2026 second-quarter results.

• Q2 total net sales of €9.3 billion, gross margin of 54.0%, net income of €2.9 billion
• ASML expects Q3 2026 total net sales between €11.0 billion and €12.0 billion, and a gross margin between 55% and 57%
• ASML now expects 2026 total net sales to be between €43 billion and €45 billion, with a gross margin between 54% and 56%

CEO statement and outlook
"Our second-quarter total net sales were €9.3 billion and gross margin came in at 54.0%, both above guidance, driven primarily by higher than expected Installed Base Management sales."

ASML Holding N.V. (ASML) today reported that Intel Foundry is using ASML's High NA EUV technology on the Intel 18A process node to produce a subset of its Intel Core Ultra Series 3 processors. This milestone marks an important step in demonstrating High NA EUV readiness in a production environment. ASML and Intel have worked closely for decades to advance lithography technology and support the continued scaling of semiconductors. The high numerical aperture extreme ultraviolet (High NA EUV) lithography process is an important next step in EUV lithography, developed by ASML to enable more precise patterning for advanced chip manufacturing.

The Intel Core Ultra Series 3 processors, code-named Panther Lake, are built on Intel 18A. The use of High NA EUV to pattern specific layers of these products provides ASML and Intel Foundry with helpful data to further refine system setup, up time and manufacturing implementation. This paves the way towards broader adoption, utilizing the full capabilities of the technology.

Chinese memory giant CXMT has been expanding its capacity so rapidly that the company is now able to compete with one of the largest memory manufacturers in the world—Micron. According to analysis from Citrini Research and their proprietary data, CXMT is projected to produce about 350,000 DRAM wafers per month by the end of 2026, assuming all current projects are completed on schedule. This is an impressive figure, especially considering that Micron, one of the "big three" DRAM manufacturers, is currently estimated to produce about 375,000 DRAM wafers per month by the end of 2026, assuming their capacity expansions are fulfilled. Micron has been a memory supplier for decades, while CXMT is a relatively new player that emerged to meet China's domestic needs.

A particularly surprising discovery is that CXMT is constructing its cleanrooms—where the actual silicon is produced—in just around 12 months, whereas the rest of the DRAM manufacturing industry typically takes 21-24 months, nearly a full year longer. The biggest challenge for Chinese memory makers like CXMT is acquiring advanced lithography solutions from around the world, as the United States government has imposed sanctions on the company and placed it on a blacklist, preventing access to modern EUV scanners. Instead, CXMT relies on older DUV lithography tools and uses multi-patterning techniques to work around the lack of EUV technology. Despite this, CXMT is matching Micron's output this year with nearly the same number of DRAM wafers, which is impressive for such a new market entrant.

South Korean giants Samsung and SK hynix have announced plans to invest about 1,350 trillion won, roughly $870 billion at the time of writing, into expanding semiconductor manufacturing capacity and data centers over the next ten years. This ten-year plan includes memory, storage, and logic, which both companies produce. For SK hynix, this investment will cover DRAM and NAND Flash, while for Samsung, it will cover DRAM, NAND Flash, as well as logic for its LSI division. The investment is so comprehensive that it will include more than just creating new fab production capacity for increased wafer output. For example, it will also encompass AI data centers, batteries, display manufacturing, chip-making tools, etching, photomasks, and much more.

The first milestone set by the South Korean government is to double DRAM production capacity within five years and significantly improve NAND Flash production capacity. By the end of the ten-year plan, both Samsung and SK hynix will add 4-5 semiconductor plants to their South Korean hubs, which will be a massive investment in job creation and production capacity. This is a strong indicator that South Korea will remain a leader in modern memory and storage production. Although the plans might seem ambitious, the ten-year timeline allows both companies and the South Korean government to manage the investment and buildout effectively.

Samsung is set to begin mass production of its 1.4 nm node in 2029, according to recent reports from South Korean media outlet The Bell. Initially, Samsung aimed for mass production in 2028, but this has been postponed to 2029 due to the expanding manufacturing capacity of the 2 nm SF2 and its derivative process, the SF2P node. This timeline aligns with the rest of the industry's targets for similar node high-volume manufacturing. Intel, for example, plans to start risk production of its 14A node in 2028, with high-volume production slated for 2029. As a result, we can expect more competitive silicon manufacturing by the end of the decade, offering better alternatives for TSMC customers. TSMC plans to begin mass production of its A14 node in 2028, which will still give it a slight time advantage over Samsung and Intel.

Additionally, it is known that Samsung is exploring High-NA EUV lithography for its 1.4 nm node, marking the company's first transition from Low-NA EUV tools in a new manufacturing process. The company has been engaging with numerous domestic suppliers as well as international toolmakers like Applied Materials and Lam Research to obtain tools for its NRD-K R&D hub for semiconductors.

According to the latest research from Morgan Stanley, one of the leading investment banks, we have learned that the defect rate for Intel's 14A node is currently reported at D0=0.5. This means that defects in Intel's 14A node production are occurring at a rate of only 0.5, indicating a limited amount of purely non-functional silicon produced during the long and challenging semiconductor manufacturing process. For Intel, this suggests that the 14A node is still in the early stages of ramping up. However, the previous claims that this node is currently surpassing the 18A node at a similar development and ramp time are indeed accurate. For example, Intel plans to target a defect rate of only 0.1 to 0.2 by the first quarter of 2027, when the company intends to start running internal test chips and initiate a slight ramp-up for its own products. This will be followed by risk production in 2028 and high-volume production in 2029.

Looking at Intel's current "Panther Lake" SoC, which integrates multiple smaller dies into a unified package, we observe that Intel has utilized its 18A node for the compute tile's production. This tile measures approximately 8.004 x 14.288 mm, resulting in a silicon area of 114.304 mm². If we take this die size and apply the current parameters of the 14A node, we can estimate that a similar die, with the same surface area but increased density and manufactured on the 14A node, would achieve a yield of 56.45% for designs of that scale. Naturally, the current 18A node is providing better yields due to high-volume manufacturing, but the initial statistics for 14A appear promising. This assumption is based on a die of that specific size, with that particular defect rate, using High-NA EUV half-field exposures in the production process. We believe this is the stage Intel's 14A node is currently at, with room for many improvements. While Morgan Stanley notes in their report that the yield is about 40% for a test chip, its size must be significantly larger than the assumed size of the "Panther Lake" compute tile.

This week, at the 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits, imec, a world-leading research and innovation hub in advanced semiconductor technologies, in partnership with the lithography solution provider ASML, and semiconductor foundry TSMC, presents a novel, robust and scalable 300 mm integration route for 2D-material based n and pFETs. For the first time, scaled nFETs (implementing MoS2 as the channel material) and pFETs (either WS2 or WSe2-based) with 50 nm contacted poly pitch (CPP) could be demonstrated, with good current-voltage characteristics. These results represent a crucial step in the lab-to-fab transition of 2D-material based transistors, envisioned for ultra-scaled logic as well as for back-end and wafer backside applications.

2D transition metal dichalcogenides (TMDs, such as MoS2, WS2, and WSe2) have the potential to extend and augment the logic scaling technology roadmap. When integrated as atomically thin conduction channels replacing Si, these materials enable high-performance scaled transistors - attractive for ultra-scaled logic as well as for back-end-of-line and wafer backside applications. They owe this promise to their good electrostatic channel control while maintaining acceptable carrier mobilities, even at ultra-scaled gate and channel lengths. But the path to industrial adoption has so far been hampered by the lack of a 300 mm integration route that can offer TMD-based n and pFETs at industry-relevant dimensions, while preserving the performance that has extensively been demonstrated on a lab scale.

Intel CEO Lip-Bu Tan spoke at the J.P. Morgan TMT Conference, providing more details about the company's roadmap for future node developments. According to Lip-Bu Tan, Intel now forecasts the 14A node risk production run in 2028, with high-volume manufacturing in 2029. This is expected to coincide with major customers ramping up their designs and starting to ship 14A silicon worldwide. Intel plans to utilize the node both internally and offer it to third-party customers, who will consume High-NA EUV exposed wafers at scale. Interestingly, the Intel CEO notes that this timeline is very similar to TSMC's A14 node, which is expected to be a direct competitor to Intel's 14A in the angstrom era of semiconductor manufacturing.

We have already reported on the progress Intel is making with 14A, noting that the node is advancing at a much better pace than Intel experienced with the 18A node. This means better yields at early stages, less complex manufacturing, and an overall improved production process. Notably, 14A is the first semiconductor node globally to utilize ASML's High-NA EUV lithography tools, which are the most sophisticated chip manufacturing machines ever designed. The 14A node is currently at the 0.5 PDK stage, and customers will finalize volume, design, and other requirements when the PDK 0.9 is released. Lip-Bu Tan expects this 0.9 PDK, which he refers to as a "holy grail," to be available in October of this year, allowing customers to start their designs.

TSMC has allocated an additional $20 billion to expand its facility in Phoenix, Arizona, at the Fab 21 site. According to the latest TSMC board resolution meeting, TSMC Arizona, a subsidiary of TSMC, will receive up to $20 billion for now, with the possibility of further capital injections in the future. This resolution supports the expansion of TSMC's Fab 21 site with additional land purchases, expensive EUV equipment, and more semiconductor manufacturing tools. The company has already invested about $65 billion in ongoing Arizona projects and pledged an additional $100 billion in capital expenditure on top of that. The total TSMC Arizona capital expenditure is projected to reach $165 billion, with parts of the additional $100 billion package being gradually unlocked, as seen in today's board meeting resolution.

Interestingly, TSMC Arizona reportedly generated about $514 million in profit last year, its first year of operations. Given TSMC's gross margins of about 66%, this suggests that Fab 21 generated approximately $1.5 billion in revenue. TSMC does not explicitly separate revenue streams from each fab publicly, but these numbers are impressive considering the fab has only been operational for a year. Typically, a fab's first-year performance is not this strong, but it seems TSMC remains an industry leader in this area as well.