TSMC has reportedly started expanding its manufacturing capacity as demand continues to outpace supply. According to a recent report from UDN, TSMC aims to increase its 2 nm manufacturing capacity at the N2 node, targeting an output of about 120,000 wafers per month by the end of 2026. This represents a 20% increase from the early August target of 100,000 wafers per month by the end of the year, indicating strong customer interest in the latest silicon technology. Even in the early stages, the company confirmed that the N2 node has four times the number of tape-outs compared to its previous leading-edge 3 nm N3 node. With the ramp-up of N2 production underway, the 20% increase suggests that customers are seeking more capacity, even as TSMC continues to scale production, indicating that demand isn't slowing down anytime soon.

At the end of the second quarter of 2026, the N2 node accounted for only 3% of TSMC's revenue, while the 3 nm node held 30%, and the 5 nm node secured the top spot at 33%. However, as we approach the end of Q3, we should see a significant shift in these figures, strongly favoring the N2 node. Until official data is released, we can't be certain of N2's exact revenue contribution, but it is expected to increase significantly based on several factors.

Fujitsu Limited today announced that it will begin global sales of its next-generation CPU, FUJITSU-MONAKA, designed and developed in Japan, starting November 2026. This will include sales of the processor as a standalone product to cloud and data center operators and server vendors. Additionally, the company will launch the made-in-Japan Fujitsu MONAKA Server equipped with the FUJITSU-MONAKA CPU, offering high reliability and power efficiency as a sovereign AI infrastructure. Fujitsu MONAKA Server will be made broadly available from November 2026 to data center operators, enterprises, and the academic and HPC sectors in Japan and Europe, as well as to the defense sector, contributing to national security.

The FUJITSU-MONAKA CPU integrates Fujitsu's extensive expertise in processor and server development, achieving world-class computational performance and data supply capabilities with a maximum operating frequency of 3.8 GHz and memory transfer speed of 8800 MT/s. It delivers twice the AI inference throughput and superior power efficiency compared to other CPUs, effectively halving the number of servers and power consumption required for equivalent processing loads.

Chinese semiconductor maker SMIC has increased its market share as the world's third-largest chipmaker. According to the latest report from TrendForce, SMIC now holds 5.4% of the semiconductor manufacturing market share in Q2 this year, a slight increase from 5.1% in Q1. In the three-month period ending in June, SMIC generated about $3 billion in revenue from domestic companies producing homegrown silicon. This marks a significant improvement compared to $2.2 billion in Q2 2025, with a slight increase in market share from that period's 5.1%. This indicates that overall capacity has increased across the supply chain.

SMIC's most advanced manufacturing nodes include the SMIC N+2, a 7 nm-class node used by Huawei to manufacture its Ascend series of AI accelerators and other infrastructure parts, and the SMIC N+3, a 5 nm-class node for its customers. The company uses DUV to print silicon designs but faces significant challenges in achieving its silicon ambitions as it currently has no access to EUV tools, since ASML has restricted exports of its EUV scanners, and it is the only company manufacturing EUV machinery at scale.

According to Reuters, Samsung Foundry is experiencing a significant increase in customer orders, prompting the company to adjust its pricing strategy across multiple nodes. In July, Samsung raised the price of its 4 nm node, known as SF4, by about 10-15% for customers in the United States and China, while customers in Taiwan saw a more modest increase of 5-10%. Prices for wafers produced with the 5 nm node, referred to as SF5, also rose by 10-15%. Interestingly, even the older 8 nm node experienced a 10% price hike. This increase for the SF8 node is likely due to NVIDIA placing orders for its GeForce RTX 3060, a product the company has reintroduced after several generations.

There is no mention of price hikes for newer nodes such as Samsung SF2, SF3, and their variations. It seems Samsung anticipated the level of external customer demand for these nodes, and they are already quite costly. Notably, Reuters reports that U.S.-based customers are prioritized after Samsung's internal chip demand for its own SoCs, while China-based design houses are third in line. However, as China seeks advanced nodes, they are willing to accept higher price increases to secure allocation at Samsung Foundry at any cost.

If readers recall, a few days ago we reported that TSMC has achieved a milestone of about 20,000 wafers per month on the company's latest 2 nm N2 node. However, the company is now rapidly scaling its high-volume manufacturing, aiming to produce about 100,000 N2 wafers per month by the end of 2026. This gives the company about four months to increase its manufacturing output fivefold. While that might seem impossible, TSMC has been rapidly scaling its manufacturing output over the years, and the latest N2 node is no exception. Currently, the N2 node accounts for only 3% of TSMC's revenue, while the 3 nm node holds 30%, and the 5 nm node secures the top spot at 33%. Even with projected growth in N3 and N5 consumption, increasing revenue fivefold would mean the N2 node would represent more than 10% of the company's overall revenue share.

Meanwhile, the demand for its 3 nm N3 family of nodes is still strong. Reportedly, TSMC's customers, including NVIDIA, AMD, Broadcom, and many others, have pushed the total monthly wafer output of the N3 node to 180,000 units, exceeding the company's internal targets. While TSMC hoped to achieve this number in the fourth quarter of 2026, demand has pushed production capacity to its limits, prompting TSMC to consider additional expansion plans for this node.

According to sources close to The Information, a Chinese company Shanghai Yuliangsheng Technology has reportedly begun limited production of immersion DUV lithography machines. This Shanghai-based company aims to produce five systems for delivery this year, with an estimated production of about 20 immersion DUV machines by 2027. While this may not seem like a large number, it represents a significant effort in developing homegrown DUV machine production, reducing reliance on third-party suppliers like ASML. The Shanghai company plans initial deliveries to SMIC, CXMT, and Hua Hong, which will integrate these machines into their production processes.

For those unfamiliar, immersion deep ultraviolet (DUV) machines use an argon-fluoride (ArF) excimer laser to produce DUV light at a 193 nm wavelength. This light travels through a layer of ultra-purified water placed above the final lens, which imprints circuit designs onto a wafer. Although this may sound straightforward, immersion DUV lithography tools are highly complex machines that ASML has been mass-producing for years. By comparison, ASML shipped 131 immersion DUV machines last year, showing the smaller scale of the Chinese production. Additionally, Chinese immersion DUV also imports some key components from Japan, while most are being sourced from China.

According to the latest information from the second quarter financial results, ASML is considering raising prices for its Low-NA EUV tools, which is reportedly upsetting its customers. ASML CFO Roger Dassen has noted that the company is looking into price increases for these tools, aligning its pricing strategy with product value. As the company continues to enhance the productivity of its tools, ASML plans to adjust pricing accordingly. The company operates a business unit called Installed Base Management, which focuses on maintaining and improving existing machines. Most of the recent productivity gains have come from ASML's software that operates EUV machines, and the company recently confirmed that:

ASML CFO Roger DassenWhen it comes to Low-NA pricing, of course, you know that we keep on increasing the productivity of the Low-NA tool. Of course, that gives us a pretty strong runway for potential price improvements going forward... Value-based pricing is the concept that we follow within ASML. In the current environment, of course, the value for customers is higher than in other circumstances.

TSMC's 2 nm node has reportedly attracted significant client attention, as the company's Senior Vice President, Kevin Zhang, confirmed that the N2 node has four times the number of tape-outs compared to its previous leading-edge 3 nm N3 node. This indicates that many of TSMC's customers, who are also long-time partners, have focused their resources on 2 nm chip designs instead of the 3 nm node PDKs. The driving force behind the fourfold increase in chip tape-outs is the impressive power and performance improvements achieved by the company's first gate-all-around FET nanosheet transistor. With GAAFET, TSMC's N2 delivers up to a 15% performance increase at the same power level, or up to a 30% power reduction at the same speed. This means designers can achieve much higher switching performance within the same power budget as the previous N3E, or reduce power consumption by nearly a third while maintaining the same performance target. Additionally, the transistor density increase is about 15%, allowing for smaller dies with the same functionality or larger dies with more performance.

Interestingly, TSMC began high-volume production of its N2 node in Q4 2025. Fast-forward two quarters to today's date, and the 2 nm node now accounts for only 3% of the company's revenue, while the 3 nm node commands 30%, and the 5 nm node holds the top spot at 33%. However, in the coming quarters, the situation is expected to change as TSMC's customers start receiving more 2 nm chips, and the node's revenue generation grows. Among the N2 customers are AMD with its EPYC "Venice" server CPUs, Apple with its A20 Pro chips for the iPhone 18 Pro series, and others. With four times as many customers using the 2 nm node compared to its 3 nm lithography, TSMC's record-breaking quarterly reports are likely to intensify. Each new node generation brings more expensive wafers due to the increasing complexity of developing a new node, so more tape-outs will significantly boost TSMC's revenue. We are yet to see just how substantial the changes will be in the next few quarters.

NextSilicon, a leader in next-generation computing solutions for AI and high-performance computing (HPC), today announced plans to productize its Arbel RISC-V core into a 64-core and a 128-core, enterprise-grade processor suited to deliver ultra-speed performance for agentic tools, expected to be available in early 2028. Following an October preview, the company is now sharing expanded technical detail and a roadmap shaped by early customer and partner feedback. This announcement coincides with NextSilicon's presentation at the RISC-V Summit.

NextSilicon designed Arbel from the ground up for the performance demands of AI infrastructure and HPC. The move from test chip to production roadmap follows customer and partner silicon evaluations, including HPC program leads, AI infrastructure architects, and data center operators. Their input has validated Arbel's key performance attributes and is shaping the requirements and architecture decisions for the 64-core production processor.

Bolt Graphics today announced the successful tape-out of its test chip, marking a key milestone in the development of its Zeus GPU. Zeus is a next-generation compute platform designed to reduce the total cost of compute by up to 17 times across high-performance computing (HPC), rendering, and emerging compute-intensive applications.

Global demand for compute capacity continues to accelerate to support capabilities such as simulations, real-time graphics, and artificial intelligence across a wide range of industries. To address the need, companies optimized existing compute architectures for peak performance rather than cost efficiency, causing infrastructure cost to become a primary constraint. As the majority of workloads remain dependent on these architectures, large segments of the available market remain economically unviable.

Samsung has developed a new SSD controller based on the open-source RISC-V instruction set, moving away from the Arm ISA in some of its SSD controllers. With the introduction of the BM9K1 PCIe 5.0 QLC NAND SSD, Samsung has officially created a proprietary RISC-V IP that will serve as a foundation for many SSDs the company plans to release. Announced at the China Flash Market Summit 2026, the BM9K1 SSD has been showcased with just one metric: sequential read speed. Achieving a maximum sequential read speed of 11.4 GB/s, Samsung has reached impressive speeds for QLC NAND Flash. While the sequential write speed is unknown, it is expected to be around 10 GB/s, varying slightly depending on Samsung's design. Typically, high-performance SSDs use TLC NAND, as seen in Samsung's own 9100 Pro SSD, which we reviewed. It features 3D TLC V-NAND V8 with 236 layers. While this SSD uses TLC NAND and has a proprietary Samsung Presto 5 nm controller running on Arm-based cores, Samsung might transition a significant portion of its SSD lineup to a RISC-V based design with the BM9K1, offering satisfactory performance with QLC NAND.

Interestingly, Samsung has designed this SSD with considerations for size, power, and AI. For instance, the BM9K1 PCIe 5.0 SSD replaces the previous BM9C1 PCIe 4.0 SSD controller. Although both use QLC NAND, the newer BM9K1 features a new RISC-V controller and a fresh PCIe 5.0 interface, doubling the performance in sequential reads on average. The power efficiency of the new RISC-V design is also improved. Samsung claims a 23% increase in power efficiency, thanks to the flexibility of RISC-V, which allows for greater customization and optimization of the controller firmware to match I/O patterns with the QLC NAND, resulting in nearly a quarter less power consumption. This improvement is expected to have a significant impact on small form factor PCs and client laptops. The main drawback of the design is the use of QLC NAND, but Samsung may introduce TLC NAND SSDs with RISC-V controllers in the future. For now, these remain on the 5 nm Presto Arm-powered controllers.

TrendForce's latest research on the foundry industry reveals that continued investment in the AI arms race by North American CSPs and AI startups will keep demand for AI processors and supporting ICs strong in 2026. Global foundry revenue is projected to grow 24.8% YoY to approximately US$218.8 billion, with TSMC expected to post the largest increase of around 32% YoY.

Demand for advanced nodes will continue to be driven by AI GPUs from companies such as NVIDIA and AMD. Meanwhile, North American CSPs, including Google, AWS, and Meta, and AI startups such as OpenAI and Groq, are accelerating the development of their own AI chips. Many of these designs are expected to enter volume production and begin shipping in 2026, becoming key drivers for 5/4 nm and more advanced process technologies.

NVIDIA has reportedly halted production of its China-focused H200 "Hopper" GPU at TSMC's facilities, according to multiple reports. The company has built up an inventory of 250,000 H200 GPUs, which will be available in the Chinese market for select applications that do not compromise United States national security. After NVIDIA was granted export rights to China for its H200 accelerators, the company began stockpiling these GPUs to supply AI labs across China. However, China has also restricted what its domestic companies and AI labs can import, meaning that the import of H200 GPUs is still prohibited unless a company receives a letter of exemption from Beijing. This has resulted in NVIDIA using its TSMC N5 5 nm node capacity to create about 250,000 units, which are now stored in a warehouse awaiting export approval from the U.S. administration and import approval from Chinese customs for AI labs.

Interestingly, the Financial Times and Reuters note that NVIDIA will now "reallocate" capacity from H200 production to the new "Rubin." However, these two GPU generations do not use the same manufacturing node or packaging technology. For "Hopper," NVIDIA uses TSMC's 5 nm node with CoWoS-S packaging, while "Rubin" uses a 3 nm node with CoWoS-L packaging. These reports likely refer to some conversion of manufacturing capacity involving either the node or packaging capacity that NVIDIA has secured. It is unlikely that the 5 nm semiconductor node can be converted into a 3 nm node without significant line remodeling and changes to manufacturing equipment. However, packaging can be adjusted more easily, which is likely what these reports are indicating.

Samsung Foundry has struck gold as its utilization rate has jumped to an impressive 80% this quarter. This comes after many years of struggling to achieve a good utilization rate, while competitors like TSMC have consistently led the adoption of newer nodes and gained a massive customer base. However, the situation has now changed, and Samsung's foundries are now operating at about 80% of total capacity, consistently producing silicon, with the Pyeongtaek Campus P2 and P3 leading the charge. Previously, these lines were only achieving a 50% booking rate last year and even struggled with insufficient production volume in the second half of 2024. Samsung uses these sites to manufacture 4 nm, 5 nm, and 7 nm nodes, which are now considered "mature," as the leading edge shifts to sub-3 nm production.

Part of the foundry revival is attributed to the strong demand for its 6th-generation HBM, coming in the form of HBM4 with a custom base die manufactured on the 4 nm node. While competitors are making HBM4 base dies on older nodes, Samsung is using a 4 nm custom base die that provides higher design density for any logic that ASIC makers want to implement. This can include some data processing that will aid the main accelerator in AI workloads. This has translated into high demand for Samsung Foundry products from external customers, who are now keeping production at high capacity.

As AI processing capabilities continue to evolve toward on-device and desktop supercomputer applications, the need for ultra-fast yet space-efficient local storage becomes increasingly important. Samsung's recent innovation in AI-optimized storage devices drives this point home. Our PM9E1 SSD—the industry's first PCIe Gen 5 4 TB SSD in M.2 22x42 form factor—complements the NVIDIA GB10-powered NVIDIA DGX Spark desktop AI supercomputer.

While AI accelerators enable systems to harness the vast power of AI, only pairing them with performance-optimized, purpose-built storage technology like the Samsung PM9E1 can provide the massive capacity and blazing access speeds to unleash that power that may lead to the development of tomorrow's killer AI apps.

Huawei's next-generation Ascend 950 AI accelerator has been pictured for the first time, showcasing the company's custom silicon and HBM memory. The chip combines Huawei's first self-developed HBM memory with a new generation of AI acceleration. Huawei aims to compete through scale rather than focusing solely on single-chip performance. Although it currently trails NVIDIA in per-chip performance, Huawei's system-scale solutions can still be competitive. The company has announced the Ascend 950 family for early 2026, featuring two variants.

The 950PR model includes 128 GB of in-house HBM with around 1.6 TB/s of bandwidth, while the 950DT model increases memory to 144 GB and boosts bandwidth to nearly 4 TB/s. Both chips target one PetaFLOP of FP8, and two PetaFLOPS of FP4. Huawei's competitive strategy emphasizes dense packaging and aggressive networking, rather than relying solely on raw per-chip performance. We have no information on the node selection, but it will likely be SMIC's newest N+3 node with 5 nm-class features. Chinese SMIC has officially achieved volume production of its newest 5 nm node relying on the deep ultraviolet (DUV) to manufacture its silicon. Since the first customer for N+3 was Huawei with Kirin 9030 SoC, it is only logical that the more important Ascend AI accelerator family is manufactured using the same node.

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects that 77 million AI PCs will ship in 2025, representing 31% of the worldwide PC market, and growing to a 55% market share in 2026. Meanwhile, edge AI is multiplying due to a variety of factors, including smaller and more efficient AI algorithms, more powerful AI silicon, and the proliferation of IoT devices.

As laptops, AI PCs, and the latest imaging systems demand even higher performance and lower power, SoCs are challenged to keep pace. Advanced-node SoCs at 5 nm and below must balance efficiency with ultra-low voltages and growing bandwidth needs. High-resolution cameras, faster frame rates, and AI-driven workloads all require interfaces that deliver speed with minimal EMI/RFI noise.

Chinese company SMIC has officially achieved volume production of its newest 5 nm-class node called SMIC N+3. This is officially China's most advanced semiconductor node produced without any extreme ultraviolet (EUV) lithography tools, relying on the deep ultraviolet (DUV) to manufacture its silicon. In the latest analysis of the Huawei Kirin 9030 SoC, the TechInsights has confirmed that the chip has officially been manufactured using the new advanced node, bringing Chinese semiconductor independence one step closer to reality. This node is a full generation ahead of the older SMIC N+2, which is 7 nm-class node Huawei has been using to manufacture its Ascend series of AI accelerators and other infrastructure parts.

However, this is not without drawbacks. Since SMIC uses DUV to print silicon designs, the company faces significant challenges in realizing its silicon ambitions. For printing smaller nodes, EUV scanners offer more possibilities due to their much smaller wavelength of 13.5 nm, compared to the smallest DUV immersion scanner wavelength of 193 nm. TechInsights has confirmed that SMIC's N+3 node, despite achieving impressive DUV multi-patterning implementation, encounters significant yield challenges, particularly due to the aggressively scaled metal pitch. As a result, the Huawei Kirin 9030 SoC is likely produced at an operating loss, with a significant portion of dies being discarded or used for downgraded chips.

NextSilicon, a startup company founded in 2017 has detailed its Maverick-2 Intelligent Compute Accelerator (ICA), claiming it outperforms NVIDIA's HGX B200 GPU and Intel's Sapphire Rapids CPUs in high-performance computing and AI workloads. Built on TSMC's 5 nm node, Maverick-2 is available as a single-die PCIe card with 96 GB of HBM3e (300 W) or a dual-die OAM version with 192 GB of HBM3e (600 W). According to internal benchmarks, Maverick-2 delivers up to 4× higher FP64 performance-per-watt than the HGX B200 and over 20× higher efficiency than Intel's Xeon Sapphire Rapids. In GUPS benchmarks, it reached 32.6 GUPS at 460 W, reportedly 22× faster than CPUs and 6× faster than GPUs. In HPCG workloads it achieved 600 GFLOPS at 750 W, while consuming roughly half the power of competing solutions. The company attributes these gains to a data-flow based architecture that shifts overhead management from hardware to adaptive software, allowing most silicon area to be used for computation rather than control logic.

Alongside Maverick-2, NextSilicon announced Arbel, a RISC-V-based enterprise-grade chip also built on TSMC's 5 nm process. The company claims Arbel already surpasses current RISC-V designs as well as Intel Lion Cove and AMD Zen 5 cores. Arbel features a 10-wide instruction pipeline with a 480-entry reorder buffer for high core utilization, running at 2.5 GHz. The chip can execute up to 16 scalar instructions in parallel and includes four 128-bit vector units for data-parallel workloads. A 64 KB L1 cache and large shared L3 cache ensure high memory throughput and low latency to reduce bottlenecks in compute-intensive applications. No release date or full benchmarks were disclosed, but NextSilicon says Arbel represents a move toward a fully open, software-adaptive silicon platform for future HPC and AI systems.

IBM (NYSE: IBM) today announced the upcoming general availability of the IBM Spyre Accelerator, an AI accelerator enabling low-latency inferencing to support generative and agentic AI use cases while prioritizing the security and resilience of core workloads. Earlier this year, IBM announced the Spyre Accelerator would be available in IBM z17, LinuxONE 5, and Power11 systems. Spyre will be generally available on October 28 for IBM z17 and LinuxONE 5 systems, and in early December for Power11 servers.

Today's IT landscape is changing from traditional logic workflows to agentic AI inferencing. AI agents require low-latency inference and real-time system responsiveness. IBM recognized the need for mainframes and servers to run AI models along with the most demanding enterprise workloads without compromising on throughput. To address this demand, clients need AI inferencing hardware that supports generative and agentic AI while maintaining the security and resilience of core data, transactions, and applications. The accelerator is also built to enable clients to keep mission-critical data on-prem to mitigate risk while addressing operational and energy efficiency.

Texas Instruments is enhancing the next generation of digital lithography with the introduction of the DLP991UUV digital micromirror device (DMD), the company's highest resolution direct imaging solution to date. With 8.9 million pixels, sub-micron resolution capabilities and a data rate of 110 gigapixels per second, the device eliminates the need for expensive mask technology while delivering the scalability, cost-effectiveness and precision needed for increasingly complex packaging.

Why it matters
Maskless digital lithography machines - which project light for etching circuit designs on materials without a photomask or high-end stencil - are becoming increasingly popular for the manufacturing of advanced packaging. Advanced packaging combines multiple chips and technologies into a single package, enabling high-computing applications, such as data centers and 5G, to have systems that are smaller, faster, and more power-efficient.

Synopsys, Inc., today announced TSMC has certified the Ansys portfolio of simulation and analysis solutions, enabling accurate final checks on chip designs targeted for TSMC's most advanced manufacturing processes including TSMC N3C, N3P, N2P, and A16. The companies also collaborated on an AI-assisted design flow for the TSMC-COUPE platform. Together, Synopsys and TSMC empower customers to effectively design chips for a range of applications including AI acceleration, high-speed communications, and advanced computing.

Multiphysics and AI-Driven Photonics Design Enablement
Synopsys continues to work with TSMC to expand multiphysics analysis flows for larger designs with hierarchical analysis methodology. The multiphysics flow includes Ansys RedHawk-SC, Ansys RedHawk-SC Electrothermal platform, and Synopsys 3DIC Compiler exploration-to-signoff platform to enable hierarchical thermal-aware timing analysis and voltage-aware timing analysis. This multiphysics approach can help customers accelerate the convergence of large 3DIC designs.

Marvell Technology, Inc., a leader in data infrastructure semiconductor solutions, today announced the Marvell Structera Compute Express Link (CXL) memory-expansion controllers and near memory compute accelerators have successfully completed interoperability testing with DDR4 and DDR5 memory solutions from industry leaders Micron Technology, Samsung Electronics, and SK hynix. This milestone follows the recent announcement "Successful Interoperability of Structera CXL Portfolio with AMD EPYC CPU and 5th Gen Intel Xeon Scalable Platforms," making Structera the only CXL 2.0 product family with completed interoperability testing across both leading CPU architectures and all three major memory suppliers.

As data-centric applications grow in complexity and memory plays a greater role in performance, interoperability is critical. Validation of Structera with DDR4 and DDR5 enables scalable system design, reduces integration risk, and streamlines qualification, while giving OEMs and cloud providers the flexibility to optimize system designs while maintaining supply chain flexibility.

AMD is reportedly sampling its next-generation Ryzen desktop processor powered by the "Zen 6" microarchitecture, codenamed "Medusa Ridge," to close industry partners, such as platform designers and OEMs, says Yuri Bubliy, aka 1usmus, author of the Hydra tuning software, and the now-retired DRAM Calculator for Ryzen. The processor sees AMD update both the CCDs and client I/O die, he says. AMD confirmed that it is building the "Zen 6" CCD on the TSMC N2 (2 nm) node, which entered risk production earlier this year. The node is expected to be ready for mass-production of 2 nm chips later this year. The 2 nm node presents a significant jump in transistor densities from the current TSMC N4P node on which AMD builds its 8-core "Zen 5" CCD, which 1usmus and other sources say, that AMD will use to increase CPU core counts per CCD.

Sources point to the possibility of AMD increasing core counts per CCD to 12, and giving the CCD 48 MB of L3 cache. At this point we don't know if all 12 cores will be arranged in a single CCX with a monolithic slab of 48 MB L3 cache, or if there's a dual-CCX layout with 6 cores per CCX sharing 24 MB of L3 cache, each. The other big upgrade with "Medusa Ridge" is its client I/O die (cIOD). AMD is expected to build its new generation cIOD on a newer EUV node such as 5 nm N5 or 4 nm N4P, a significant upgrade from the current 6 nm N6. 1usmus says that the biggest reason for AMD to update its cIOD is the memory controller architecture. AMD is expected to give "Medusa Point" a new dual memory controller architecture. There are still two DDR5 channels per socket, but this is redesigned for increased memory speeds, letting AMD catch up with Intel in this area. As for the CPU frequency boosting technologies, such as PBO and Curve Optimizer, there are no updates expected, and 1usmus concludes that it Hydra support should be straightforward.

Xsight Labs, a leading fabless semiconductor company providing end-to-end connectivity for next-generation hyperscale, edge and AI data center networks, today announced availability of its Arm -based E1-SoC for cloud and edge AI data centers. The E-Series is the only product of its kind to provide full control plane and data path programmability and is the industry's highest performance software-defined DPU (Data Processing Unit). Xsight Labs is taking orders now for its E1-SoC and the E1-Server, the first-to-market 800G DPU.

E1 is the first SoC in the E-Series, Xsight Labs' SDN (Software Defined Network) Infrastructure Processor product family of fully programmable network accelerators. Built on TSMC's advanced 5 nm process technology, the E1-SoC will begin shipping to customers and ecosystem partners.