Both AMD and Intel have said IPC uplifts by 2025 will be at least 70% compared today. It's no surprise at all to see 20% IPC increase each gen and others have said it might be closer to 30% with Zen 4. 2025 is only 3 more gens at most, so 1.2^3 = 1.728. So 20% uplift per gen compared to previous gen, is 72% over 3 generations basically what they said.

MLiD is not stating anything that isn't already known IMO if you can believe AMD and Intel.

Minus InfinityBoth AMD and Intel have said IPC uplifts by 2025 will be at least 70% compared today. It's no surprise at all to see 20% IPC increase each gen and others have said it might be closer to 30% with Zen 4. 2025 is only 3 more gens at most, so 1.2^3 = 1.728. So 20% uplift per gen compared to previous gen, is 72% over 3 generations basically what they said.

While I haven't seen them commit to a specific number, it is highly likely that we will see an IPC gain of >50% in the next five years or so. Just continuing to extend the instruction window, add some more execution ports etc. still have more potential for ILP, even though it's getting harder.

As we continue to advance, we will be facing diminishing returns as we scale towards cache misses and branch predictions. But that's not the end of the line for single threaded performance, we can scale much further if we mitigate the causes of the pipeline stalls, especially considering the relative cost of a pipeline stall is increasing as the CPU gets wider execution. I know Intel is researching "threadlets", and AMD is probably experimenting as well. If they manage to engineer a solution which avoids completely stalling and limits the scope of pipeline flushes, they could unleash a sizable performance gain, and probably result in IPC gains in the range of ~2-3x.