Sunday, June 12th 2022

Intel "Meteor Lake-P" SoC with 6P+8E Compute Tile Pictured

Intel's next-generation "Meteor Lake-P" mobile processor with a 6P+8E Compute Tile was shown off at the 2022 IEEE VLSI Symposium on Tech and Circuits (6 performance cores and 8 efficiency cores). We now have annotations for all four tiles, as well as a close-up die-shot of the Compute Tile. Intel also confirmed that the Compute Tile will be built on its homebrew Intel 4 silicon fabrication process, which offers over 20% iso-power performance increase versus the Intel 7 node, through extensive use of EUV lithography.

We had earlier seen a 2P+8E version of the "Meteor Lake" Compute Tile, probably from the "Meteor Lake-U" package. The larger 6P+8E Compute tile features six "Redwood Cove" performance cores, and two "Crestmont" efficiency core clusters, each with four E-cores. Assuming the L3 cache slice per P-core or E-core cluster is 2.5 MB, there has to be 20 MB of L3 cache on the compute tile. Each P-core has 2 MB of dedicated L2 cache, while each of the two E-core clusters shares 4 MB of L2 cache among four E-cores.
Elsewhere in the SoC, we see the three other tiles—the iGPU Tile (dubbed GFX Tile), the SoC Tile, and the I/O tile. The GFX Tile packs the iGPU, which is possibly a more power-dense component than even a P-core, and so this tile very likely gets the most advanced silicon fabrication node on the package, which is very likely the TSMC N3 (3 nm). The SoC Tile packs uncore and high-bandwidth I/O components, including the memory controllers, PCI-Express 5.0 root complex, Management Engine, etc.

The I/O Tile is essentially an integrated PCH that handles platform I/O that isn't as bandwidth heavy has the main PEG interface, or the main Gen 5 NVMe interface. This tile could be built on the least advanced fabrication process. All four tiles are placed on a silicon interposer through 3D Foveros technology. The interposer is a silicon die that facilitates high-density microscopic wiring between dies in a multi-chip module; and appears like a single contiguous die to the fiberglass substrate.
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13 Comments on Intel "Meteor Lake-P" SoC with 6P+8E Compute Tile Pictured

#1
Crackong
May I ask what is 'iso-power performance' mean?
Posted on Reply
#3
ghazi
What on earth is that image? One view shows the compute in the middle, the other shows SOC in the middle. And what the hell is there a separate IO die from the "SOC" for?
Posted on Reply
#4
Crackong
ChaitanyaMost likely related to this: ieeexplore.ieee.org/document/6012831
So in terms of these P series processers, assume 25W power consumption, it will give me the performance of Alder Lake P running at 30W ?
Posted on Reply
#5
Tomorrow
Does not matter much if it's late like all Intel's products lately.
Posted on Reply
#6
Minus Infinity
ghaziWhat on earth is that image? One view shows the compute in the middle, the other shows SOC in the middle. And what the hell is there a separate IO die from the "SOC" for?
Huh, the last image is just the close up image of the compute unit. The image was taken with a camera at an Intel event where the press were invited
Posted on Reply
#7
Gungar
ghaziWhat on earth is that image? One view shows the compute in the middle, the other shows SOC in the middle. And what the hell is there a separate IO die from the "SOC" for?
Probably just to have smaller silicon pieces, to reduce cost.
Posted on Reply
#8
Valantar
CrackongMay I ask what is 'iso-power performance' mean?
"Iso" used in this way means (roughly) "the same", so 'iso-power performance' means 'performance at the same level of power draw'.

20% increased performance at the same power and 2x area scaling is pretty impressive - but then this should also be more than a full node improvement, considering most competitors have several steps in between 7 and 4 (not that the numbers are anything more than marketing, but they are meant to be roughly indicative of general characteristics at least). It'll definitely be interesting to see how this plays out in real life.
Posted on Reply
#9
DeathtoGnomes
Valantar"Iso" used in this way means (roughly) "the same", so 'iso-power performance' means 'performance at the same level of power draw'.

20% increased performance at the same power and 2x area scaling is pretty impressive - but then this should also be more than a full node improvement, considering most competitors have several steps in between 7 and 4 (not that the numbers are anything more than marketing, but they are meant to be roughly indicative of general characteristics at least). It'll definitely be interesting to see how this plays out in real life.
TBF, Intel has a habit of overestimating performance improvements. It will be interesting indeed, but dont hold your breath.
Posted on Reply
#10
ghazi
Minus InfinityHuh, the last image is just the close up image of the compute unit. The image was taken with a camera at an Intel event where the press were invited
I mean the diagram vs the "package photo". Not the close up of the CPU die. Compare the arrangement of the chiplets, it's contradictory. I really wonder how Intel screws up a slide like that.
GungarProbably just to have smaller silicon pieces, to reduce cost.
Sure, but the "SOC" itself is mostly just I/O to begin with... so what specifically goes on the I/O die? Maybe they want to put the IMC on a more performant node than the slower I/O.
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#11
Psyclown
Man all these cores, cores and more cores. Intel should have stuck with Netburst. We’d be up to 100 Ghz by now with an 80 stage pipeline on one core.
Posted on Reply
#12
Valantar
PsyclownMan all these cores, cores and more cores. Intel should have stuck with Netburst. We’d be up to 100 Ghz by now with an 80 stage pipeline on one core.
And each PC would come with a portable nuclear reactor to put in your garage!
Posted on Reply
#13
Psyclown
ValantarAnd each PC would come with a portable nuclear reactor to put in your garage!
See Netburst would have ushered in a new era of nuclear reactor use as well. And it also would have heated my whole house. It really was a jack of all trades.
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Jun 28th, 2022 19:56 EDT change timezone

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