Wednesday, September 20th 2023

TSMC Could Delay 2 nm Mass Production to 2026

According to TechNews.tw, TSMC could postpone its 2 nm semiconductor manufacturing node for 2026. If the rumors about TSMC's delayed 2 nm production schedule are accurate, the implications could reverberate throughout the semiconductor industry. TSMC's alleged hesitancy could be driven by multiple factors, including the architectural shift from FinFET to Gate-All-Around (GAA) and potential challenges related to scaling down to 2 nm. The company is a crucial player in this space, and a delay could offer opportunities for competitors like Samsung, which has already transitioned to GAA transistor architecture for its 3 nm chips. Given the massive demand for advanced nodes due to the rise of AI, IoT, and other next-gen technologies, it is surprising to hear "sluggish" demand reports.

However, it's also possible that it's too early for customers to make firm commitments for 2025 and beyond. TSMC has dismissed these rumors, stating that construction is progressing according to plan, which includes having 2 nm pilot run in 2024, and mass production in the second half of 2025.. Despite this, any delay in TSMC's roadmap could serve as a catalyst for shifts in market dynamics. Companies that rely heavily on TSMC's advanced nodes might need to reassess their timelines and strategies. Moreover, if Samsung can capitalize on this opportunity, it could somewhat level the playing field. As of now, though, it's essential to approach these rumors with caution until more concrete information becomes available.
Source: TechNews.tw
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35 Comments on TSMC Could Delay 2 nm Mass Production to 2026

#26
bug
AnotherReaderFor a very long time, Intel kept delivering a new process every two years while everyone else fell further and further behind after 130 nm. It wasn't until 22 nm that Intel started having trouble keeping to that cadence though the delays weren't significant at that node. Despite how it's remembered, 14 nm was the first Intel node that had a major slip.
Makes you wonder: did they lose talent over time or did they keep the talent, but grew overconfident?
Posted on Reply
#27
ARF
Prima.VeraIs 2nm actual size, or is just a marketing name, like O2, or something?
What is the real size and how does it compare to competition I wonder? (Such as Intel's 18A, for example)
intel's 20A and 18A are closer to TSMC N3 node, I suspect.
You can find the specifications (or part of them) in wiki en.wikipedia.org/wiki/3_nm_process

And I asked uncle google about the first part of your question, and it said:
Increasingly advanced semiconductor generations are called process nodes. Each process node represents a set of feature sizes; the smaller a chip’s features are, the more transistors it can contain, allowing it to execute more complex tasks. While the names of these nodes (e.g., 250 nanometers, nm) were historically based on approximate distances between parts of the chip, they are more arbitrary “branding” specifications today. In 2022, the most advanced mass-produced process node was the 5 nm node, with larger-scale 3 nm manufacturing expected soon. On the other hand, chips designed to more mature process nodes (e.g., 90 nm) are called legacy chips.
bipartisanpolicy.org/blog/understanding-chips-part-1/
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#28
AnotherReader
bugMakes you wonder: did they lose talent over time or did they keep the talent, but grew overconfident?
I doubt anyone outside Intel knows. It's conjectured that they became complacent because of their huge lead. They also aimed too high with 10 nm, now known as Intel 7, and would probably have benefitted from the TSMC approach of smaller and more frequent node transitions.
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#29
bug
AnotherReaderI doubt anyone outside Intel knows. It's conjectured that they became complacent because of their huge lead. They also aimed too high with 10 nm, now known as Intel 7, and would probably have benefitted from the TSMC approach of smaller and more frequent node transitions.
That's exactly what lack of talent or overconfidence will do to you. There's also the possibility of competent people taking a calculated risk, but seeing how hard that hit Intel, it's pretty clear there wasn't anything calculated about that.
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#30
Wirko
AnotherReaderI doubt anyone outside Intel knows. It's conjectured that they became complacent because of their huge lead. They also aimed too high with 10 nm, now known as Intel 7, and would probably have benefitted from the TSMC approach of smaller and more frequent node transitions.
It's amazing that the "Lake" design team also fell asleep when it should double its efforts. They must have known well in advance that 10nm wouldn't reach mass production until 2021. They had the opportunity to make a lot of small architectural improvements in the meantime, also peeking over the shoulders of the "Cove" design team, which was very much active. But no. The 10th gen of Intel CPUs wasn't Skylake++ on 14nm++, it was still Skylake on 14nm++.
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#31
bug
WirkoIt's amazing that the "Lake" design team also fell asleep when it should double its efforts. They must have known well in advance that 10nm wouldn't reach mass production until 2021. They had the opportunity to make a lot of small architectural improvements in the meantime, also peeking over the shoulders of the "Cove" design team, which was very much active. But no. The 10th gen of Intel CPUs wasn't Skylake++ on 14nm++, it was still Skylake on 14nm++.
That is also contingent on how the fab team communicated their status to the other teams. And that's not public info.
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#32
AnotherReader
bugThat's exactly what lack of talent or overconfidence will do to you. There's also the possibility of competent people taking a calculated risk, but seeing how hard that hit Intel, it's pretty clear there wasn't anything calculated about that.
Given that they dominated the semiconductor industry until then, I doubt it was a lack of talent. Overconfidence is probably a factor, but sometimes even big companies make the wrong bet. Using Cobalt for the two smallest wiring layers in the 10 nm process is suspected to be the biggest issue for that process. Cobalt is a difficult material to work with. This is also supported by Intel 4 switching to a Copper alloy for the five smallest metal layers.

Posted on Reply
#33
bug
AnotherReaderGiven that they dominated the semiconductor industry until then, I doubt it was a lack of talent. Overconfidence is probably a factor, but sometimes even big companies make the wrong bet. Using Cobalt for the two smallest wiring layers in the 10 nm process is suspected to be the biggest issue for that process. Cobalt is a difficult material to work with. This is also supported by Intel 4 switching to a Copper alloy for the five smallest metal layers.

The way I read it, it was going for quad pattering instead of the usual triple that did them in. But it doesn't really matter at this point.
Posted on Reply
#34
AnotherReader
bugThe way I read it, it was going for quad pattering instead of the usual triple that did them in. But it doesn't really matter at this point.
Anyone outside Intel won't know the full story, but that was probably a key factor too.
Posted on Reply
#35
mahirzukic2
Vayra86Still not news lol.
Did you miss Intel 10nm? TSMC 7? EUV?

The context is that every node ever has been a delayed/staggered launch and in practice it means every time you get access to it far later than anyone 'roadmapped' for.
That just goes to show you that all these companies make very ambitious and non-realistic roadmaps.
The same happened in most of the companies I have worked for.
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