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Global Chip Shortage Takes Another Toll... Now Your Home Router?

The global supply of semiconductor processors has been at risk lately. Starting from GPUs to CPUs, the demand for both has been much greater than the available supply. Manufacturing companies, such as TSMC, have been expanding capacities, however, they have not yet been able to satisfy the demand. We have seen the results of that demand in a form of the scarcity of the latest generation of graphics cards, covering NVIDIA's GeForce RTX 3000 series Ampere, and AMD' Radeon RX 6000 series Big Navi graphics cards. Consumers have had a difficult time sourcing them and they have seen artificial price increase that is much higher than their original MSRP.

However, it doesn't seem like the situation will improve. According to the latest reporting from Bloomberg, the next victim of global chip shortage is... you guessed it, your home internet router. The cited sources have noted that the waiting list to get a batch of ordered routers has doubled the waiting time, from the regular 30 weeks to 60-week waiting time. This represents a waiting list that is more than a year long. With the global COVID-19 pandemic still going strong, there is an increased need for better home router equipment, and delays can only hurt broadband providers that supply routers. Taiwan-based router manufacturer Zyxel Communications, notes that the company has seen massive demand for their equipment. Such a massive demand could lead to insufficient supply, which could increase prices of routers well above their MSRP and bring scarcity of them as well.

Raja Koduri Teases "Petaflops in Your Palm" Intel Xe-HPC Ponte Vecchio GPU

Raja Koduri of Intel has today posted an interesting video on his Twitter account. Showing one of the greatest engineering marvels Intel has ever created, Mr. Koduri has teased what is to come when the company launches the Xe-HPC Ponte Vecchio graphics card designed for high-performance computing workloads. Showcased today was the "petaflops in your palm" chip, designed to run AI workloads with a petaflop of computing power. Having over 100 billion transistors, the chip uses as much as 47 tiles combined in the most advanced packaging technology ever created by Intel. They call them "magical tiles", and they bring logic, memory, and I/O controllers, all built using different semiconductor nodes.

Mr. Koduri also pointed out that the chip was born after only two years after the concept, which is an awesome achievement, given that the research of the new silicon takes years. The chip will be the heart of many systems that require massive computational power, especially the ones like AI. Claiming to have the capability to perform quadrillion floating-point operations per second (one petaflop), the chip will be a true monster. So far we don't know other details like the floating-point precision it runs at with one petaflop or the total power consumption of those 47 tiles, so we have to wait for more details.
More pictures follow.

AMD to Supply Only a Few Thousand Radeon RX 6700 XT GPUs for Europe at Launch

The global supply chain of graphics cards is currently not very well equipped to handle the massive demand that exists for the latest generation of GPUs. Just like we have seen with the launch of NVIDIA GeForce RTX 3000 series Ampere, and AMD Radeon RX 6000 series Big Navi SKUs, the latest generation graphics cards are experiencing massive demand. And manufacturers of these GPUs are not very well equipped to handle it all, so there is a huge scarce for GPUs in the global market. With AMD's recent announcement of the Radeon RX 6700 XT graphics card, things are not looking any better, and the availability of this GPU could be very tight at launch.

According to information obtained by Igor's Lab, AMD could supply only a few thousand Radeon RX 6700 XT GPUs for Europe as a whole. To be precise, Igor's Lab notes that "If you condense the information of various board partners and distributors to a trend, then there are, depending on the manufacturer and model, only a few pieces (for Germany) to a few thousand for the EU as a whole." This could be a very bad indication of AMD's supply of these new GPUs globally, not just for Europe. The company is currently relying on the overbooked TSMC, which can only produce a limited amount of chips at the time, and we don't know how much capacity AMD allocated for the new chip.

GLOBALFOUNDRIES 22FDX RF Solution Provides the Basis for Next-Gen mmWave Automotive Radar

GLOBALFOUNDRIES (GF ), the global leader in specialty semiconductor manufacturing, and Bosch will partner to develop and manufacture next-generation automotive radar technology.

Bosch chose GF as its partner to develop a mmWave automotive radar system-on-chip (SoC) for Advanced Driver Assistance Systems (ADAS) applications, manufactured using GF's 22FDX RF solution. ADAS applications help drivers stay safe by keeping a vehicle in the correct lane, warning of collisions, initiating emergency braking, assisting with parking, and more.

SiPearl to Manufacture its 72-Core Rhea HPC SoC at TSMC Facilities

SiPearl has this week announced their collaboration with Open-Silicon Research, the India-based entity of OpenFive, to produce the next-generation SoC designed for HPC purposes. SiPearl is a part of the European Processor Initiative (EPI) team and is responsible for designing the SoC itself that is supposed to be a base for the European exascale supercomputer. In the partnership with Open-Silicon Research, SiPearl expects to get a service that will integrate all the IP blocks and help with the tape out of the chip once it is done. There is a deadline set for the year 2023, however, both companies expect the chip to get shipped by Q4 of 2022.

When it comes to details of the SoC, it is called Rhea and it will be a 72-core Arm ISA based processor with Neoverse Zeus cores interconnected by a mesh. There are going to be 68 mesh network L3 cache slices in between all of the cores. All of that will be manufactured using TSMC's 6 nm extreme ultraviolet lithography (EUV) technology for silicon manufacturing. The Rhea SoC design will utilize 2.5D packaging with many IP blocks stitched together and HBM2E memory present on the die. It is unknown exactly what configuration of HBM2E is going to be present. The system will also see support for DDR5 memory and thus enable two-level system memory by combining HBM and DDR. We are excited to see how the final product looks like and now we wait for more updates on the project.

Industry Specialists Expect Chip Shortages to Last Until 2022

Industry specialists with various analysis groups have stated that they expect the world's current chip supply shortages to not only fail to be mitigated in the first half of 2021, but that they might actually last well into 2022. It's not just a matter of existing chip supply being diverted by scalpers, miners, or other secondary-market funnels; it's a matter of fundamental lack of resources and production capacity to meet demand throughout various quadrants of the semiconductor industry. With the increased demand due to COVID-19 and the overall increasingly complex design of modern chips - and increased abundance of individual chips within the same products - foundries aren't being able to scale their capacity to meet growing demand.

As we know, the timeframe between start and finish of a given semiconductor chip can sometimes take months. And foundries have had to extend their lead times (the time between a client placing an order and that order being fulfilled) already. This happens as a way to better plan out their capacity allocation, and due to the increased complexity of installing, testing, and putting to production increasingly complex chip designs and fabrication technologies. And analysts with J.P. Morgan and Susquehanna that are in touch with the pulse of the semiconductor industry say that current demand levels are 10% to 30% higher than those that can be satisfied by the fabrication and supply subsystems for fulfilling that demand.

AMD Instinct MI200 to Launch This Year with MCM Design

AMD is slowly preparing the next-generation of its compute-oriented flagship graphics card design called Instinct MI200 GPU. It is the card of choice for the exascale Frontier supercomputer, which is expected to make a debut later this year at the Oak Ridge Leadership Computing Facility. With the supercomputer planned for the end of this year, AMD Instinct MI200 is also going to get launched eight a bit before or alongside it. The Frontier exascale supercomputer is supposed to bring together AMD's next-generation Trento EPYC CPUs with Instinct MI200 GPU compute accelerators. However, it seems like AMD will utilize some new technologies for the making of this supercomputer. While we do not know what Trento EPYC CPUs will look like, it seems like Instinct MI200 GPU is going to feature a multi-chip-module (MCM) design with the new CDNA 2 GPU architecture. With this being the only information about the GPU, we have to wait a bit to find out more details.
AMD CDNA Die

Microchip Announces World's First PCI Express 5.0 Switches

Applications such as data analytics, autonomous-driving and medical diagnostics are driving extraordinary demands for machine learning and hyperscale compute infrastructure. To meet these demands, Microchip Technology Inc. today announced the world's first PCI Express (PCIe) 5.0 switch solutions—the Switchtec PFX PCIe 5.0 family—doubling the interconnect performance for dense compute, high speed networking and NVM Express (NVMe ) storage. Together with the XpressConnect retimers, Microchip is the industry's only supplier of both PCIe Gen 5 switches and PCIe Gen 5 retimer products, delivering a complete portfolio of PCIe Gen 5 infrastructure solutions with proven interoperability.

"Accelerators, graphic processing units (GPUs), central processing units (CPUs) and high-speed network adapters continue to drive the need for higher performance PCIe infrastructure. Microchip's introduction of the world's first PCIe 5.0 switch doubles the PCIe Gen 4 interconnect link rates to 32 GT/s to support the most demanding next-generation machine learning platforms," said Andrew Dieckmann, associate vice president of marketing and applications engineering for Microchip's data center solutions business unit. "Coupled with our XpressConnect family of PCIe 5.0 and Compute Express Link (CXL ) 1.1/2.0 retimers, Microchip offers the industry's broadest portfolio of PCIe Gen 5 infrastructure solutions with the lowest latency and end-to-end interoperability."

Apple Patents Multi-Level Hybrid Memory Subsystem

Apple has today patented a new approach to how it uses memory in the System-on-Chip (SoC) subsystem. With the announcement of the M1 processor, Apple has switched away from the traditional Intel-supplied chips and transitioned into a fully custom SoC design called Apple Silicon. The new designs have to integrate every component like the Arm CPU and a custom GPU. Both of these processors need good memory access, and Apple has figured out a solution to the problem of having both the CPU and the GPU accessing the same pool of memory. The so-called UMA (unified memory access) represents a bottleneck because both processors share the bandwidth and the total memory capacity, which would leave one processor starving in some scenarios.

Apple has patented a design that aims to solve this problem by combining high-bandwidth cache DRAM as well as high-capacity main DRAM. "With two types of DRAM forming the memory system, one of which may be optimized for bandwidth and the other of which may be optimized for capacity, the goals of bandwidth increase and capacity increase may both be realized, in some embodiments," says the patent, " to implement energy efficiency improvements, which may provide a highly energy-efficient memory solution that is also high performance and high bandwidth." The patent got filed way back in 2016 and it means that we could start seeing this technology in the future Apple Silicon designs, following the M1 chip.

Update 21:14 UTC: We have been reached out by Mr. Kerry Creeron, an attorney with the firm of Banner & Witcoff, who provided us with additional insights about the patent. Mr. Creeron has provided us with his personal commentary about it, and you can find Mr. Creeron's quote below.

TSMC to Put Away More Capacity for Automotive Industry if Possible

TSMC is one of the world's biggest semiconductor manufacturers, and the company is currently the leading provider of the newest technologies like 5 nm and 3 nm, along with advanced packaging. So far, TSMC's biggest customers have included Apple, NVIDIA, AMD, etc., where the company has mainly produced chips for mobile phones and PCs/Servers. However, Taiwan's Economics Ministry has announced that they have spoken to TSMC and have reached an agreement that the company will be putting away some additional capacity for the automotive industry, specifically for the production of automotive chips. The reason for this push is the increasing shortage of semiconductors for automakers, experienced due to the Trump administration sanctions against key Chinese chip factories.

TSMC has stated that "Other than continuously maximizing utilization of our existing capacity, Dr. Wei also confirmed in our investors' conference that we are working with customers closely and moving some of their mature nodes to more advanced nodes, where we have a better capacity to support them". The company also states that their capacities are fully utilized for now, however, TSMC has ensured ministry that "if production can be increased by optimizing production capacity, it will cooperate with the government to regard automotive chips as a primary application." That means that TSMC will not decrease any existing capacity, but rather just evaluate any increased capacity for automotive chip production.

AMD is Allegedly Preparing Navi 31 GPU with Dual 80 CU Chiplet Design

AMD is about to enter the world of chiplets with its upcoming GPUs, just like it has been doing so with the Zen generation of processors. Having launched a Radeon RX 6000 series lineup based on Navi 21 and Navi 22, the company is seemingly not stopping there. To remain competitive, it needs to be in the constant process of innovation and development, which is reportedly true once again. According to the current rumors, AMD is working on an RDNA 3 GPU design based on chiplets. The chiplet design is supposed to feature two 80 Compute Unit (CU) dies, just like the ones found inside the Radeon RX 6900 XT graphics card.

Having two 80 CU dies would bring the total core number to exactly 10240 cores (two times 5120 cores on Navi 21 die). Combined with the RDNA 3 architecture, which brings better perf-per-watt compared to the last generation uArch, Navi 31 GPU is going to be a compute monster. It isn't exactly clear whatever we are supposed to get this graphics card, however, it may be coming at the end of this year or the beginning of the following year 2022.

Intel CEO Says Using Competitor's Semiconductor Process in Intel Fabs is an Option

Semiconductor manufacturing is not an easy feat to achieve. Especially if you are constantly chasing the smaller and smaller node. Intel knows this the best. The company has had a smooth transition from other nodes to the smaller ones until the 10 nm node came up. It has brought Intel years of additional delay and tons of cost improving the yields of a node that was seeming broken. Yesterday the company announced the new Tiger Lake-H processors for laptops that are built using the 10 nm process, however, we are questioning whatever Intel can keep up with the semiconductor industry and deliver the newest nodes on time, and with ease. During an interview with Intel's CEO Bob Swan, we can get a glimpse of Intel's plans for the future of semiconductors at the company.

In the interview, Mr. Swan has spoken about the technical side of Intel and how the company plans to utilize its Fabs. The first question everyone was wondering was about the state of 10 nm. The node is doing well as three Fabs are ramping up capacity every day, and more products are expected to arrive on that node. Mr. Swan has also talked about outsourcing chip production, to which he responded by outlining the advantage Intel has with its Fabs. He said that outsourcing is what is giving us shortages like AMD and NVIDIA experience, and Intel had much less problems. Additionally, Mr. Swan was asked about the feasibility of new node development. To that, he responded that there is a possibility that Intel could license its competitor's node and produce it in their Fabs.

Hedge Fund Urges Intel to Outsource Chip Production: Reuters

Intel is familiar with chip manufacturing problems since the company started the development of a 10 nm silicon semiconductor node. The latest node is coming years late with many IPs getting held back thanks to the inability of the company to produce it. All of Intel's chip production was historically happening at Intel's facilities, however, given the fact that the demand for 14 nm products is exceeding production capability, the company was forced to turn to external foundries like TSMC to compensate for its lack of capacity. TSMC has a contract with Intel to produce silicon for things like chipsets, which is offloading a lot of capacity for the company. Today, thanks to the exclusive information obtained by Reuters, we have information that a certain New York hedge fund, Third Point LLC, is advising the company about the future of its manufacturing.

The hedge fund is reportedly accounting for about one billion USD worth of assets in Intel, thus making it a huge and one influencing shareholder. The Third Point Chief Executive Daniel Loeb wrote a letter to Intel Chairman Omar Ishrak to take immediate action to boost the company's state as a major provider of processors for PCs and data centers. The company has noted that Intel needs to outsource more of its chip production to satisfy the market needs, so it can stay competitive with the industry. The poor performance of Intel has reflected on the company shares, which have declined about 21% this year. This has awoken the shareholders and now we see that they are demanding more aggressiveness from the company and a plan to outsource more of the chip production to partner foundries like TSMC and Samsung. It remains to be seen how Intel responds and what changes are to take place.

NVIDIA to Introduce an Architecture Named After Ada Lovelace, Hopper Delayed?

NVIDIA has launched its GeForce RTX 3000 series of graphics cards based on the Ampere architecture three months ago. However, we are already getting information about the next-generation that the company plans to introduce. In the past, the rumors made us believe that the architecture coming after Ampere is allegedly being called Hopper. Hopper architecture is supposed to bring multi-chip packaging technology and be introduced after Ampere. However, thanks to @kopite7kimi on Twitter, a reliable source of information, we have data that NVIDIA is reportedly working on a monolithic GPU architecture that the company internally refers to as "ADxxx" for its codenames.

The new monolithically-designed Lovelace architecture is going make a debut on the 5 nm semiconductor manufacturing process, a whole year earlier than Hopper. It is unknown which foundry will manufacture the GPUs, however, both of NVIDIA's partners, TSMC and Samsung, are capable of manufacturing it. The Hopper is expected to arrive sometime in 2023-2024 and utilize the MCM technology, while the Lovelace architecture will appear in 2021-2022. We are not sure if the Hopper architecture will be exclusive to data centers or extend to the gaming segment as well. The Ada Lovelace architecture is supposedly going to be a gaming GPU family. Ada Lovelace, a British mathematician, has appeared on NVIDIA's 2018 GTC t-shirt known as "Company of Heroes", so NVIDIA may have already been using the ADxxx codenames internally for a long time now.

NVIDIA is Preparing Co-Packaged Photonics for NVLink

During its GPU Technology Conference (GTC) in China, Mr. Bill Dally—NVIDIA's chief scientist and SVP of research—has presented many interesting things about how the company plans to push the future of HPC, AI, graphics, healthcare, and edge computing. Mr. Dally has presented NVIDIA's research efforts and what is the future vision for its products. Among one of the most interesting things presented was a plan to ditch the standard electrical data transfer and use the speed of light to scale and advance node communication. The new technology utilizing optical data transfer is supposed to bring the power required to transfer by a significant amount.

The proposed plan by the company is to use an optical NVLink equivalent. While the current NVLink 2.0 chip uses eight pico Joules per bit (8 pJ/b) and can send signals only to 0.3 meters without any repeaters, the optical replacement is capable of sending data anywhere from 20 to 100 meters while consuming half the power (4 pJ/b). NVIDIA has conceptualized a system with four GPUs in a tray, all of which are connected by light. To power such a setup, there are lasers that produce 8-10 wavelengths. These wavelengths are modulated onto this at a speed of 25 Gbit/s per wavelength, using ring resonators. On the receiving side, ring photodetectors are used to pick up the wavelength and send it to the photodetector. This technique ensures fast data transfer capable of long distances.

AWS and Arm Demonstrate Production-Scale Electronic Design Automation in the Cloud

Today, Amazon Web Services, Inc. (AWS), an Amazon.com, Inc. company, announced that Arm, a global leader in semiconductor design and silicon intellectual property development and licensing, will leverage AWS for its cloud use, including the vast majority of its electronic design automation (EDA) workloads. Arm is migrating EDA workloads to AWS, leveraging AWS Graviton2-based instances (powered by Arm Neoverse cores), and leading the way for transformation of the semiconductor industry, which has traditionally used on-premises data centers for the computationally intensive work of verifying semiconductor designs.

To carry out verification more efficiently, Arm uses the cloud to run simulations of real-world compute scenarios, taking advantage of AWS's virtually unlimited storage and high-performance computing infrastructure to scale the number of simulations it can run in parallel. Since beginning its AWS cloud migration, Arm has realized a 6x improvement in performance time for EDA workflows on AWS. In addition, by running telemetry (the collection and integration of data from remote sources) and analysis on AWS, Arm is generating more powerful engineering, business, and operational insights that help increase workflow efficiency and optimize costs and resources across the company. Arm ultimately plans to reduce its global datacenter footprint by at least 45% and its on-premises compute by 80% as it completes its migration to AWS.

Intel Debuts 2nd-Gen Horse Ridge Cryogenic Quantum Control Chip

At an Intel Labs virtual event today, Intel unveiled Horse Ridge II, its second-generation cryogenic control chip, marking another milestone in the company's progress toward overcoming scalability, one of quantum computing's biggest hurdles. Building on innovations in the first-generation Horse Ridge controller introduced in 2019, Horse Ridge II supports enhanced capabilities and higher levels of integration for elegant control of the quantum system. New features include the ability to manipulate and read qubit states and control the potential of several gates required to entangle multiple qubits.

"With Horse Ridge II, Intel continues to lead innovation in the field of quantum cryogenic controls, drawing from our deep interdisciplinary expertise bench across the Integrated Circuit design, Labs and Technology Development teams. We believe that increasing the number of qubits without addressing the resulting wiring complexities is akin to owning a sports car, but constantly being stuck in traffic. Horse Ridge II further streamlines quantum circuit controls, and we expect this progress to deliver increased fidelity and decreased power output, bringing us one step closer toward the development of a 'traffic-free' integrated quantum circuit."-Jim Clarke, Intel director of Quantum Hardware, Components Research Group, Intel.

TSMC Partners With Google and AMD to Push 3D Silicon

Silicon manufacturing is starting to get harder and harder every day, with new challenges appearing daily. It requires massive investment and massive knowledge to keep a silicon manufacturing company afloat. No company can survive that alone, so some collaborations are emerging. Today, thanks to the sources of Nikkei Asia, we have information that Taiwanese Semiconductor Manufacturing Company (TSMC) is collaborating with Google to push the production of 3D chip manufacturing process, that is said to overcome some of the silicon manufacturing difficulties. The sources also say that AMD is involved in the process as well, making Google and AMD the first customers of the advanced 3D chip design. The two companies are preparing designs for the new way of creating silicon and will help TSMC test and certify the process.

TSMC will deploy the 3D silicon manufacturing technology at its chip packaging plant in Miaoli, which is supposed to do mass production in 2022. With Google and AMD being the first customers of new 3D technology, it is exciting to see what new products will look like and how they will perform. The 3D approach is said to bring huge computing power increase, however, it is a waiting game now to see how it will look like.

Marvell Announces Industry's First 112G 5nm SerDes Solution for Scaling Cloud Data Center Infrastructure

Marvell today unveiled the industry's first 112G 5 nm SerDes solution that has been validated in hardware. The DSP-based SerDes boasts industry-leading performance, power and area, helping to propel 112G as the interconnect of choice for next generation 5G, enterprise, and cloud data center infrastructure. Marvell has recently secured a new custom ASIC design win customer that will embed this new IP to build next generation top-of-rack (ToR) and spine switches for leading hyperscale data centers around the world. The Marvell 5 nm SerDes solution doubles the bandwidth of current systems based on 56G while enabling the deployment of 112G I/Os in many exciting new applications, including network and data center switching, network traffic management, machine learning training and inference, and application-specific accelerators.

Today's news, which comes on the heels of the company's announcement with TSMC of its 5 nm portfolio, further strengthens Marvell's leading data infrastructure offerings in the industry's most advanced process geometry. The 112G 5 nm SerDes solution is part of Marvell's industry-leading IP portfolio that addresses the full spectrum of infrastructure requirements and includes processor subsystems, encryption engines, system-on-chip fabrics, chip-to-chip interconnects, and a variety of physical layer interfaces.

Samsung's 5 nm Node in Production, First SoCs to Arrive Soon

During its Q3 earnings call, Samsung Electronics has provided everyone with an update on its foundry and node production development. In the past year or so, Samsung's foundry has been a producer of a 7 nm LPP (Low Power Performance) node as its smallest node. That is now changed as Samsung has started the production of the 5 nm LPE (Low Power Early) semiconductor manufacturing node. In the past, we have reported that the company struggled with yields of its 5 nm process, however, that seems to be ironed out and now the node is in full production. To contribute to the statement that the new node is doing well, we also recently reported that Samsung will be the sole manufacturer of Qualcomm Snapdragon 875 5G SoC.

The new 5 nm semiconductor node is a marginal improvement over the past 7 nm node. It features a 10% performance improvement that is taking the same power and chip complexity or a 20% power reduction of the same processor clocks and design. When it comes to density, the company advertises the node with x1.33 times increase in transistor density compared to the previous node. The 5LPE node is manufactured using the Extreme Ultra-Violet (EUV) methodology and its FinFET transistors feature new characteristics like Smart Difusion Break isolation, flexible contact placement, and single-fin devices for low power applications. The node is design-rule compatible with the previous 7 nm LPP node, so the existing IP can be used and manufactured on this new process. That means that this is not a brand new process but rather an enhancement. First products are set to arrive with the next generation of smartphone SoCs, like the aforementioned Qualcomm Snapdragon 875.

AMD in Talks with Partners About Custom Radeon RX 6900 XT Designs

Just a few days ago AMD has announced its Radeon RX 6000 series of graphics cards based on the new RDNA 2 architecture. While AMD has given out the "Big Navi" chips to its partners to design custom boards and give users designs with better cooling and possibly higher overclocking capabilities, that doesn't seem to extend to the highest-end parts. So far, we have seen custom designs from companies like ASUS, MSI, etc., and all of them have one thing in common - they only do designs for Radeon RX 6800 or RX 6800 XT. So one would wonder where are the highest-end custom Radeon RX 6900 XT designs.

The first wave of the "custom" cards will be on November 18th, when manufacturers will release designs that are MBA (Made-by-AMD), meaning that the PCB is a reference design, just with a custom cooler installed. When it comes to the custom RX 6900 XT cards, AMD is now in talks with its partners whether to keep the biggest "Big Navi" design available for custom designs, or to keep it as AMD exclusive, with the most likely scenario being the AMD exclusivity. AMD partners could carry the models in their stores and offerings, however, the PCB and cooler design would be AMD's. The situation is yet unresolved so we have to wait and see what comes out of it and if we are getting any custom designs of the Radeon RX 6900 XT model.

Apple A14 SoC Put Under the Microscope; Die Size, and Transistor Density Calculated

Apple has established itself as a master of silicon integrated circuit design and has proven over the years that its processors deliver the best results, generation after generation. If we take a look at the performance numbers of the latest A14 Bionic, you can conclude that its performance is now rivaling some of the x86_64 chips. So you would wonder, what is inside this SoC that makes it so fast? That is exactly what ICmasters, a semiconductor reverse engineering and IP services company, has questioned and decided to find out. For starters, we know that Apple manufactures the new SoCs on TSMC's N5 5 nm node. The Taiwanese company promises to pack 171.3 million transistors per square millimeter, so how does it compare to an actual product?

ICmasters have used electron microscopy to see what the chip is made out of and to measure the transistor density. According to this source, Apple has a chip with a die size of 88 mm², which packs 11.8 billion N5 transistors. The density metric, however, doesn't correspond to that of TSMC. Instead of 171.3 million transistors per mm², the ICmasters measured 134.09 million transistors per mm². This is quite a difference, however, it is worth noting that each design will have it different due to different logic and cache layout.
Apple A14 SoC Die Apple A14 SoC

AMD Updates its Chipset Drivers, Includes Updated Power Plan for Ryzen CPUs

In the anticipation of the AMD Ryzen 5000 series of CPUs launch based on Zen 3 architecture, AMD has just released the updated drivers for its chipsets. Covering a wide selection ranging from B350, A320, X370, X399, B450, X470, X570, B550, and TRX40 Chipset, the updated chipset drivers include some bug fixes and new features. Now there is an updated power plan for AMD Ryzen CPUs that coordinate with chipsets, which means that AMD engineers have developed a new plan for Windows 10 OS which provides the best performance and power usage. You can check out the fixes listed below and you can go to the download link to install the new drivers.
Download: AMD Ryzen Chipset Driver 2.10.13.408.

ASUS Seemingly Drops Support for AMD Ryzen 5000 Series CPUs on X470 Motherboards, the Company Responds

Today there is some quite interesting information circulating the web regarding ASUS and its alleged decision. Going a few months back, AMD released a statement regarding the support for its upcoming Ryzen 5000 series CPUs and said that it should enable compatibility with the last-generation X470 and B450 chipset. That, however, has remained a bit of mystery. The update is baked-in with the BIOS, which every manufacturer, like MSI, ASUS, Gigabyte, etc. provides independently of AMD. So it is a manufacturer-dependant case, where if one vendor chooses not to provide support for 400 series chipsets, many motherboards will not support new CPU generation.

Update Oct 14th: ASUS has reached out to us and said that "ASUS will provide updated BIOS' for the X470 and B450 chipsets based on AMD's current release schedule of new AGESA code in January 2021. This original report was based on incorrect information." This means that the customer support case contained wrong information, and ASUS is going to support 5000 series Ryzen CPUs on 400 series chipsets. Please note that the information below is incorrect.

Arm Highlights its Next Two Generations of CPUs, codenamed Matterhorn and Makalu, with up to a 30% Performance Uplift

Editor's Note: This is written by Arm vice president and general manager Paul Williamson.

Over the last year, I have been inspired by the innovators who are dreaming up solutions to improve and enrich our daily lives. Tomorrow's mobile applications will be even more imaginative, immersive, and intelligent. To that point, the industry has come such a long way in making this happen. Take app stores for instance - we had the choice of roughly 500 apps when smartphones first began shipping in volume in 2007 and today there are 8.9 million apps available to choose from.

Mobile has transformed from a simple utility to the most powerful, pervasive device we engage with daily, much like Arm-based chips have progressed to more powerful but still energy-efficient SoCs. Although the chip-level innovation has already evolved significantly, more is still required as use cases become more complex, with more AI and ML workloads being processed locally on our devices.
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