Tuesday, November 26th 2024

YMTC Produces up to 500,000 Wafers Per Year of Leading-Edge NAND Memory

Chinese semiconductor memory giant YMTC is reportedly manufacturing anywhere between 400-500,000 wafers per year of leading-edge NAND memory, all on domestically produced wafers. According to Mayuki Hashimoto, CEO and Chairman of SUMCO, a Japanese company supplying raw silicon ingots and polished wafers, they are seeing a significant business impact stemming from China's growing self-reliance, especially with companies like YMTC producing its own silicon ingots and polished wafers. This has led to SUMCO's decreasing revenue, where the CEO shared some insights about Chinese ambitions. He added that China is producing about one million wafers of silicon per year, most of which are test wafers. This includes test runs from companies like SMIC and its customers, such as T-Head, HiSilicon, and others.

Last year, YMTC, with its Xtacking 4.0 3D NAND flash architecture, was the first company to achieve a 200+ layer count in the 3D NAND space. The company's product, X4-9070, a 232-layer TLC 3D NAND, uses multiple silicon wafers, hence growing its massive consumption of silicon that is projected to reach 500,000 wafers per year. Given that this is all homegrown silicon from ingots to NAND, this is a massive success for Chinese self-reliance efforts but a huge blow to companies that used to supply Chinese firms with raw materials. Although the company uses custom silicon, it still relies on foreign tools, photoresists, and pre-cursors. There are some indications that YMTC is developing its own tools; it is a plan of a broader strategy in the Chinese semiconductor industry to develop every step of the semiconductor manufacturing process. Huawei is also there to develop EUV scanners, and YMTC could help with its memory business, which is in need of a new tool.
Source: via Dylan Patel (SemiAnalysis)
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6 Comments on YMTC Produces up to 500,000 Wafers Per Year of Leading-Edge NAND Memory

#1
kondamin
How many layers are made on one wafer Before they get stacked?
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#2
AleksandarK
News Editor
kondaminHow many layers are made on one wafer Before they get stacked?
No idea, YTMC didn't say that anywhere IIRC.
Posted on Reply
#3
Caring1
I can't be the only one here that thought of this group :laugh:
Posted on Reply
#4
Calenhad
kondaminHow many layers are made on one wafer Before they get stacked?
I always thought a wafer was one layer. Since the component is "drawn" on it during manufacturing. BUT I am not an expert on this and cba to search for more details.
Caring1I can't be the only one here that thought of this group :laugh:
Same here :roll:
Posted on Reply
#5
Wirko
AleksandarKNo idea, YTMC didn't say that anywhere IIRC.
It's in the TPU article that you linked to, and is yours too:
According to the documentation obtained by Tom's Hardware, YMTC has developed two SKUs based on the upgraded Xtacking 4.0: X4-9060, a 128-layer three-bit-per-cell (TLC) 3D NAND, and the X4-9070, a 232-layer TLC 3D NAND. By using string stacking on both of these SKUs, YMTC plans to make the 3D NAND work by incorporating arrays with 64 and 116 active layers stacked on top of each other.
They make 116 layers on each wafer, then they stack two dies, which is called string stacking. Whether the wafer is cut into dies before or after that, I don't know. All manufacturers seem to use string stacking.
Posted on Reply
#6
AleksandarK
News Editor
WirkoIt's in the TPU article that you linked to, and is yours too:


They make 116 layers on each wafer, then they stack two dies, which is called string stacking. Whether the wafer is cut into dies before or after that, I don't know. All manufacturers seem to use string stacking.
Nice catch Ive briefly skimmed over it to just link it. Thanks for the heads up! :)
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Dec 8th, 2024 15:29 CST change timezone

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