Researchers at the Fraunhofer Institute for Photonic Microsystems IPMS have developed a new compact package for their 2K OLED microdisplay. The microdisplay package integrates MIPI DSI-2 control and the generation of all required display voltages. The new solution will be presented for the first time at SEMICON Europa 2026 from November 10 to 13, 2026, in Munich - at the Silicon Saxony joint booth in Hall B1, Booth B1-221-25.

OLED microdisplays are frequently used in portable applications such as helmets and smart glasses as well as in optical devices. The new microdisplay package simplifies the integration of Fraunhofer IPMS's 2K microdisplays into such systems, as it combines the microdisplay with the complete electronics required for its control. An integrated 20 mm x 20 mm system-on-module (SoM) implements the MIPI DSI-2 interface via D-PHY, which is widely used in mobile processors and transmits image data and control commands serially at high speeds. The microdisplay package supports up to four data lanes with a data rate of up to 2.5 Gbit/s per lane.

Diamond Foundry Inc. today announced a major milestone in the history of materials technology: the creation of the first-ever D200mm single-crystal diamond, measuring 200 millimeters in diameter. The achievement marks a fundamental step forward in humanity's ability to manufacture diamond as a technology material at semiconductor-relevant scale.

Diamond has long been recognized as an extraordinary material for technology. It combines the highest thermal conductivity with exceptional mechanical strength, electrical insulation, optical properties, and the potential for extreme electronic performance. Yet its use in advanced technology has been constrained by one basic limitation: size. Diamond Foundry's D200mm breakthrough changes that.

The SEMI Silicon Manufacturers Group (SMG) reported today, in its quarterly analysis of the silicon wafer industry, that worldwide silicon wafer shipments increased 13.4% year-on-year to 3,756 million square inches (MSI) from the 3,313 MSI recorded during the same quarter of 2025. Shipments increased 5.1% quarter-over-quarter from the 3,573 MSI recorded during the second quarter of 2026.

"Silicon wafer shipments increased in the third quarter, supported by strong AI-related demand and improving industrial demand," said Masatsugu Miura, Chairman of SEMI SMG and General Manager of Sales & Marketing Department of Sales & Marketing Division at SUMCO Corporation. "AI-related demand continued to broaden beyond advanced logic and memory to include power devices and photonics. Industrial demand strengthened, supported by robotics, AI server power supplies and improving demand for general-purpose industrial semiconductors. Bonding and advanced packaging applications also continued to support demand for 300 mm polished wafers."

Qualcomm has officially validated its High Bandwidth Compute (HBC) concept, which the company showcased this summer. Instead of using traditional HBM and compute dies, Qualcomm has developed a technology that stacks multiple LPDDR layers and embeds a base die that serves as a compute engine for AI inference. In Qualcomm's San Diego lab, the first-generation HBC has achieved silicon validation with full read-write and near-memory computation capabilities. HBC utilizes LPDDR memory, stacking it across multiple layers in a 3D vertical space and interconnecting them with through-silicon vias (TSVs). This approach provides better energy efficiency than traditional HBM, which stacks regular DDR in vertical layers, as the low-power DDR (LPDDR) chips consume less power while delivering similar bandwidth and capacity.

Qualcomm has successfully stacked multiple LPDDR layers on top of each other, with the base of the HBC being a compute die that performs near-memory computation and offloads processing to near-memory dies. This technique is similar to what HBM4 memory currently does, with the base die being a logic die to better integrate compute solutions for packet tracing and data preparation for entering and exiting HBM. However, Qualcomm aims to achieve higher efficiency and more optimized data movement, with a 6x increase in bandwidth per watt compared to the current HBM specification. The goal is to have compute directly under these memory stacks so that data travels only a few microns instead of a few centimeters.

Earlier this month, leakers claimed NVIDIA had stopped allocating GB202 silicon to the GeForce RTX 5090, effectively discontinuing the Blackwell flagship. NVIDIA denied it a few days later, with SVP Jeff Fisher saying the RTX 5090 hasn't been discontinued and will keep shipping. Now, Moore's Law Is Dead (MLID) says the plans are still in place, and the RTX 5080 is part of them too. In the latest Broken Silicon episode, MLID read out a message from what he calls one of his oldest sources, apparently a major retailer, saying NVIDIA has set discontinuation dates for both cards in the first half of January 2027.

According to that source, the last RTX 5090 shipments arrived in September, while the final RTX 5080 batch should land by the end of October and sell through Thanksgiving. We recently reported that Micro Center has already marked its RTX 5090 listings as "Not Carried," which could be further evidence of the RTX 5090 leaving shelves. The retailer from MLID's video also says its system already has a placeholder SKU for an RTX 5080 24 GB, which aligns with BenchLife's earlier report of a Q1 2027 launch.

Today, IBM (NYSE: IBM), in collaboration with Siemens, announced new research aimed at advancing IBM's nanostack architecture, a new transistor architecture unveiled by IBM earlier this year. The collaboration will bring together IBM's leadership in semiconductor device innovation and Siemens' expertise in electronic design automation (EDA), process simulation, lithography optimization, and advanced manufacturing software to accelerate the development of nanostack.

Nanostack is the industry's first known three-dimensional, nanosheet-based design, vertically stacking and staggering transistors to pack more transistors onto a chip, with nearly 100 billion transistors in a space the size of a fingernail at its current 7 angstrom node. The design also unlocks the use of different material combinations within each stacked layer to optimize performance and power efficiency of each transistor independent of the other. These innovations power substantial leaps in energy efficiency, performance, and SRAM scaling.

NVIDIA has reportedly stopped allocating GB202 silicon to the GeForce RTX 5090, according to leaker MEGAsizeGPU (@Zed__Wang) on X. "No more GB202 for 5090, confirmed," the leaker posted, adding in a follow-up that "all future GB202 supplies are RTX Pro exclusive." GB202 is the largest "Blackwell" graphics chip, and the RTX 5090 doesn't even max it out. The same chip powers the 96 GB RTX PRO 6000 with 24,064 CUDA cores, as well as the recently unveiled RTX PRO 5500, which pairs the RTX 5090's 21,760 CUDA cores with 84 GB of memory. Apparently, NVIDIA would rather put every GB202 it gets into those far pricier workstation cards. The company hasn't confirmed any of this as of the time of writing.

A second leaker, hongxing2020, posted "5090 EOL, 5080 24GB ready" alongside an apparent factory notice saying NVIDIA will no longer sell any RTX 5090 model, China-market D variants included. The same notice says an RTX 5080 24 GB will become the top GeForce card and the 16 GB version will be discontinued. That sounds a lot like the RTX 5080 SUPER, which was rumored with 24 GB of GDDR7 on the same GB203 chip, although it isn't clear if the two are the same card. SUPER cards reportedly reached board partners in July, only to be put on hold over GDDR7 pricing. As for the RTX 5090, I doubt NVIDIA would formally call this an end-of-life (EOL) move, since the chips are simply being redirected to a more profitable product line.

Rapidus Corporation today announced that it will establish the Rapidus Collaborative Open Rapid Ecosystem (CORE), a global ecosystem framework to support the development and mass production of cutting-edge semiconductors.

Today, semiconductor development requires more than just manufacturing technology; it is essential to integrate the entire semiconductor value chain—including research institutions, EDA, IP, design and manufacturing—to provide customers with a development and production infrastructure they can rely on. Further, amid a global shortage of cutting-edge semiconductor talent, it is crucial to build a design ecosystem that enables customers to begin development at an early stage by collaborating with design-related companies.

Synopsys, Inc. (Nasdaq: SNPS) today announced a strategic agreement with Amazon to accelerate Amazon's custom silicon innovation and advance the development of increasingly complex AI-powered products and cloud infrastructure. The multi-year agreement marks the expansion of Synopsys' silicon IP business to serve increasing demand for application-optimized IP with Amazon as its lead customer.

Amazon continues to build on its leadership and longstanding investment in a broad portfolio of purpose-built chips, including Nitro for cloud security, network and storage, Graviton for general-purpose computing, and Trainium for AI training and inference workloads. Building on more than 15 years of collaboration, the agreement expands Amazon's use of Synopsys' IP to include application-optimized silicon IP. The agreement also expands Amazon's use of Synopsys EDA, simulation and analysis (S&A), and agentic AI technologies. Synopsys and Amazon will work to accelerate multiphysics solutions on Trainium and Graviton.

Meet the ultimate aluminium mechanical keyboard designed to bring your setup an entirely new level of performance and style. The YUNZII AL98 PRO combines a productivity-friendly 96% layout with 100 keys and a multifunctional knob, powerful Dual 8K polling rate, gasket mount, hot-swappable PCB, an 8000mAh battery, and seamless tri-mode connectivity via 2.4G wireless, USB-C wired, and Bluetooth. With fully customizable key mapping, macros, RGB, and profiles, every detail can be tailored to your preferences.

Wrapped in a full-aluminium body, the AL98 PRO delivers a premium look and solid feel, available in three timeless colors: White, Black, and Pink. It also comes with Double-Shot PBT & PC Cherry Profile keycaps, extra accent keycaps for easy style changes, and a soft silicone wrist rest for added comfort. Whether you're gaming, working, coding, or building your dream desk setup, the AL98 PRO is designed to do it all.

HRL Laboratories published a quantum computing milestone in Nature today: a quantum processor that runs itself. Quantum computers normally depend on racks of external electronics to generate every control signal. HRL replaced those racks with a custom control chip that sits near the qubits, in the extreme cold. The combined system autonomously ran error correction, an essential routine for any future quantum computer.

HRL's approach addresses a central obstacle for all quantum computing platforms: how to control the enormous number of qubits that a useful machine will require without an unmanageable tangle of wiring and electronics.

GlobalFoundries announced today that the United States Government, under the administration of Donald J. Trump, has signed a letter of intent with the U.S. Department of Commerce to advance next-generation silicon photonics technologies. Notably, GlobalFoundries will receive $300 million from the CHIPS Act fund, while the U.S. Government will acquire approximately a 1% equity stake in the company. As some may recall, GlobalFoundries ceased its efforts in leading-edge node research, development, and manufacturing just as the industry was transitioning to 7 nm. However, the company has since shifted its focus to other technologies, such as silicon photonics, which are becoming increasingly valuable in the era of AI expansion.

GlobalFoundries stated that this funding will be used to develop next-generation silicon photonics and advanced packaging, focusing on near-packaged optics (NPO), co-packaged optics (CPO), 3D hybrid bonding, and novel material development. The company recently introduced its SCALE (Silicon Photonics Co-Packaged Advanced Light Engine) platform, which supports 400 Gb/s package transfers with high energy efficiency. They plan to invest these R&D funds in their manufacturing facilities in Malta, New York, and Burlington, Vermont, fulfilling their commitment to develop manufacturing capabilities on U.S. soil.

The SEMI Silicon Manufacturers Group (SMG) reported today, in its quarterly analysis of the silicon wafer industry, that worldwide silicon wafer shipments increased 7.4% year-on-year to 3,573 million square inches (MSI) from the 3,327 MSI recorded during the same quarter of 2025. Shipments increased 9.1% quarter-over-quarter from the 3,275 MSI recorded during the first quarter of 2026.

"Silicon wafer shipments maintained steady growth in the second quarter, driven by strong and increasing AI-related demand beyond advanced logic and memory to include power devices, photonics, and other markets," said Ginji Yada, Chairman of SEMI SMG and Managing Executive Officer, General Manager, Sales and Marketing Division at SUMCO Corporation. "In addition, industrial and automotive demand is recovering, while memory price pressures are contributing to constrained PC and smartphone demand. Device manufacturers are investing heavily in capacity expansion, and silicon wafer demand growth is expected to continue."

Cadence's AI-driven digital and custom reference flows, tools, and solutions are now certified on Intel 18A-P and Intel 14A technologies, based on the latest Intel Foundry process design kits (PDKs). Building on the companies' recent expansion of design IP optimized for Intel 18A and 18A-P and their multi-year Design Technology Co-Optimization (DTCO) agreement targeting Intel 14A, this new certification provides customers with a signoff-ready path to deploy advanced AI, high performance computing (HPC), and mobile SoCs on Intel Foundry's leading-edge nodes.

Cadence has worked closely with Intel Foundry to co-optimize tools, flows, and methodologies that fully leverage the innovations in Intel 18A, Intel 18A-P, and Intel 14A, including RibbonFET gate-all-around transistors and advanced backside power delivery technologies such as PowerVia and PowerDirect. By tightly coupling process capabilities with Cadence's agentic AI-driven EDA portfolio and high-performance design IP, customers can achieve industry-leading power, performance, and area (PPA) while reducing design risk and time to market.

The complexity of modern chip design continues to grow as engineering teams work to develop increasingly sophisticated CPUs, GPUs and AI systems. To help meet that challenge, NVIDIA is collaborating with industry leaders Cadence and Synopsys to optimize critical electronic design automation (EDA) applications for the NVIDIA Vera CPU. NVIDIA is now deploying Vera across EDA workflows used to develop its next generation of CPUs and GPUs, demonstrating how high-performance CPU architecture can help accelerate some of the industry's most demanding engineering workloads.

Accelerating Critical EDA Workloads
What's at stake is the pace of chip production. In turn, the tempo of industry technologies that stand to benefit from boosted EDA workloads, driving development momentum. Simulation, verification and implementation technologies play a central role in semiconductor development. Long before a chip reaches manufacturing, engineers spend years validating behavior, identifying corner cases and refining designs through thousands of iterations. While GPUs and AI have accelerated many aspects of chip design, several critical EDA workloads remain heavily dependent on CPU performance. Logic simulation, formal verification and portions of digital implementation often depend on fast individual cores, efficient memory systems and strong overall throughput. That makes CPU architecture an important factor in determining how quickly engineering teams can validate designs, explore alternatives and move products toward tapeout.

European semiconductor independence has been a hot topic recently, and European Union lawmakers, particularly the European Commission, have passed the Chips Act 2.0 to achieve semiconductor manufacturing independence from the rest of the world. Now, only a week after the law has been passed, a German startup has raised capital to work on power semiconductors for next-generation electric vehicles. NexiGO, a Berlin-based startup, aims to focus on Gallium Oxide (Ga₂O₃) to power most of the power electronics needed across Europe. Starting with a €2 million pre-seed funding round, NexiGO plans to tackle the challenge of charging electric vehicles. The company intends to allow much higher voltage band gaps and enable vehicle charging to occur in just 10 minutes, significantly less time than the current 60-minute average achieved with Silicon Carbide or Gallium Nitride.

Interestingly, NexiGO will produce Gallium Oxide semiconductors on epitaxial wafers that are up to 4 inches in size, which is a third of the size of traditional logic and memory wafers made in the 12-inch format. The company has likely assessed that this size is sufficient to manufacture Gallium Oxide at a scale that satisfies domestic electricity transmission needs. For example, charging stations require an ultra-wide bandgap semiconductor to handle massive power surges with little to no loss. Standard semiconductors can't sustain the large voltage, while Gallium Oxide has a bandgap of roughly 4.8 eV, allowing for much lower energy loss in power transmission.

Apple has recently overhauled its entire M-Series chip plans, scrapping the launch of the M6 Pro and M6 Max processors and jumping straight to the M7 series. While the base M6 SoC is expected to launch, Apple is moving into the M7 series without the M6 Pro/Max variants, with plans to offer some of the most powerful computing solutions in the market. Apple is testing the M6 SoC in the base MacBook Pro model, featuring many improvements in CPU microarchitecture and NPU performance for local AI processing. Reportedly, memory is also being upgraded for higher bandwidth, now targeting around 200 GB/s, up from 123 GB/s in the current base M5 SoC. The integrated GPU will see a 20% increase in core count, featuring 12 GPU cores in the M6, which will be a noticeable improvement from the current 10-core configuration in the M5.

However, Bloomberg's Mark Gurman, in the PowerOn newsletter, confirmed that Apple's plans for the M7 Ultra chip include much faster local AI with more CPU, GPU, and NPU power, as well as a total memory capacity of 1.5 TB, a configuration only seen on the Mac Pro desktop systems. Next year's base M7 processor is expected to arrive in the first half of 2027 and will also upgrade memory bandwidth to about 240 GB/s. This is supposed to be the first Intel-manufactured Apple Silicon design, utilizing the 18A-P node. The M7 Pro and M7 Max will arrive in late 2027 with much higher bandwidth and performance. An M7 Ultra version will follow in 2028 for Mac Studio, which will be a 1.5 TB DRAM machine. With that unified memory, local model development and heavier tasks will be supported without hassle.

Qualcomm Technologies, Inc. (NASDAQ: QCOM) today announced at its Investor Day, new data center solutions, including the Qualcomm Dragonfly C1000 CPU, Qualcomm High Bandwidth Compute (HBC), Qualcomm Dragonfly AI300 inference accelerator, and connectivity products, together with custom silicon solutions, all engineered to maximize performance per watt and token throughput at lower total cost of ownership. The new platforms highlight Qualcomm Technologies' growing role in building full-stack data center infrastructure optimized for AI, spanning agentic and data-center-class CPUs, AI inference accelerators, high-performance connectivity, and at scale custom silicon solutions. The Qualcomm Dragonfly AI300 joins the previously announced Qualcomm Dragonfly AI200 and AI250 in its data center solutions portfolio with an annual cadence AI accelerator roadmap.

"Agentic AI is driving a significant increase in demand for AI inference in the data center. As these become the dominant workloads, infrastructure has to deliver much higher performance at lower power and cost," said Cristiano Amon, President and CEO, Qualcomm Incorporated. "That plays directly to Qualcomm's strengths, and we're well positioned for this shift. With Qualcomm Dragonfly, we're bringing our high-performance, low-power computing into the data center, with multi-year, multi-generation agreements with leading customers."

NextSilicon, a leader in next-generation computing solutions for AI and high-performance computing (HPC), today announced plans to productize its Arbel RISC-V core into a 64-core and a 128-core, enterprise-grade processor suited to deliver ultra-speed performance for agentic tools, expected to be available in early 2028. Following an October preview, the company is now sharing expanded technical detail and a roadmap shaped by early customer and partner feedback. This announcement coincides with NextSilicon's presentation at the RISC-V Summit.

NextSilicon designed Arbel from the ground up for the performance demands of AI infrastructure and HPC. The move from test chip to production roadmap follows customer and partner silicon evaluations, including HPC program leads, AI infrastructure architects, and data center operators. Their input has validated Arbel's key performance attributes and is shaping the requirements and architecture decisions for the 64-core production processor.

Building on more than 30 years of collaboration, Applied Materials, Inc. today announced a new innovation partnership with TSMC to accelerate the development and commercialization of semiconductor technologies required for the next era of AI. Working together at Applied's EPIC Center in Silicon Valley, the companies will co-innovate to advance materials engineering, equipment innovation, and process integration technologies designed to deliver energy-efficient performance from the data center to the edge.

"Applied and TSMC share a long history of deep collaboration built on trust and a shared commitment to advancing innovation at the leading edge of semiconductor technology," said Gary Dickerson, President and CEO of Applied Materials. "By bringing our teams together at the EPIC Center, we are strengthening that partnership and accelerating the development of technologies to address the unprecedented complexity driving the chip making roadmap."

It's no secret that Apple's $599 MacBook Neo has been a hit for general productivity workflows and as a Chromebook replacement, but in a recent financial results report, Tim Cook touched on just how unexpectedly high the Neo's demand was. The outgoing CEO on April 30 confirmed that Apple was supply-constrained on the MacBook Neo, explaining that "we under-called the level of enthusiasm that would be with it." In a recent report, industry analyst, Tim Culpan claimed that insider sources report that Apple has ordered a fresh production run on the A18 Pro SoC that powers the MacBook Neo from TSMC.

Crucially, getting TSMC to spin up a new production run of the A18 Pro may affect the pricing of the Neo, since its initial production run used rejected A18 Pro SoCs—with a defective GPU core—from the original iPhone 16 Pro smartphones, and a new run of SoCs would mean that Apple would be subject to the same memory supply constraints as the rest of the industry instead of using up old inventory that had already been paid for at a lower price. This news also comes after wild rumors of a potentially incoming MacBook Neo with an A19 Pro from the newer iPhone 17 Pro, replete with a potential 12 GB RAM upgrade. The fresh SoCs from TSMC, however, would allow Apple to reach its new 10 million unit production goal without changing anything about the hardware itself.

Rambus Inc. (NASDAQ: RMBS), a premier chip and silicon IP provider making data faster and safer, today announced the Rambus PCIe 7.0 Switch IP with Time Division Multiplexing (TDM), a new addition to its advanced interconnect IP portfolio designed to address the rapidly escalating bandwidth, latency, and scalability requirements of AI, cloud, and high-performance computing (HPC) systems.

As AI infrastructure grows in scale and architectural complexity, system designers are increasingly challenged to move massive volumes of data efficiently across CPUs, GPUs, accelerators, and NVMe storage. The Rambus PCIe 7.0 Switch IP with TDM is architected to help meet these demands by enabling more flexible and efficient utilization of PCIe links, supporting emerging disaggregated and pooled compute architectures while maintaining low latency and deterministic performance.

Companies like Apple are always seeking top-tier manufacturing for their Apple Silicon products, which range from the A-Series chips in iPhones and low-power MacBooks to the more powerful M-Series SoCs that power iPads and higher-end Macs. Manufacturing these custom processors has traditionally been handled by TSMC, but Bloomberg now reports that Apple has been in talks with both Intel Foundry and Samsung Foundry to manufacture some of its chips in the coming months. It has been known for some time that Apple is exploring Intel's 18A-P process design kits (PDKs). Apple has used version 0.9.1 of the PDK designed for Intel's 18A-P node. With performance, density, power, and other metrics meeting expectations, Intel could become Apple's source for advanced node production by 2027.

Additionally, Apple is reportedly waiting for Intel to release the 18A-P PDK version 1.0, which is on track to launch in the first half of 2026 or may have already been released to partners. Once available, Apple plans to start with the lowest-end M-series chip, used in MacBook Air and iPad Pro devices, as previously mentioned. This node is particularly interesting due to its performance characteristics, as the 18A-P can deliver a 9% performance increase at the same power level or achieve 18% power savings at the same performance level compared to the standard 18A. This is exactly what Apple is looking for. Coupled with better thermal conductivity, these designs should offer improved heat dissipation and performance compared to what Apple currently achieves with TSMC's 3 nm process in the M5 SoC.

The SEMI Silicon Manufacturers Group (SMG) reported today, in its quarterly analysis of the silicon wafer industry, that worldwide silicon wafer shipments increased 13.1% year-on-year to 3,275 million square inches (MSI) from the 2,896 MSI recorded during the same quarter of 2025. Sequentially, shipments declined 4.7% quarter-over-quarter from the 3,437 MSI recorded during the fourth quarter of 2025 in line with typical seasonality.

"Silicon wafer demand related to AI data centers continues to be strong, including advanced logic and memory, and also now extending to power management devices," said Ginji Yada, Chairman of SEMI SMG and Managing Executive Officer, General Manager, Sales and Marketing Division at SUMCO Corporation. "Overall, silicon wafer demand has improved, but the recovery is not uniform. Many device companies have noted improvements in the industrial semiconductor segment, and this is creating a more broad-based recovery as wafer inventory is absorbed. Weaker smartphone and PC shipments in the first quarter of this year may show the impact of tighter supply of memory due to AI high bandwidth memory (HBM) allocation decisions."

We have been reporting on the intense demand in the CPU sector currently sweeping the industry. AMD and Intel have sold out their inventories, and lead times are now weeks long. However, Intel, which manufactures a large part of its CPU portfolio, has been handling the situation differently. According to Intel and confirmed by industry analyst Ben Bajarin, the company is repurposing some of the dies found on the very edge of the silicon wafer, which would have otherwise become silicon scrap, into products that customers are eager to buy. This approach allows even some SKUs, which may have been flawed due to various effects like silicon node yield, to find new life through repurposing. Intel's customers are so eager for CPUs that higher-end parts, which would typically be discarded, are now being sold as independent SKUs. No silicon is left behind.

For example, when Intel produces a Xeon 6 "Granite Rapids" CPU on the Intel 3 node, the CPU compute die can accommodate up to 44 cores per die, but some are disabled for yield and power reasons. When the yield fails, these compute dies are repurposed into SKUs with lower core counts, as it costs Intel money to manufacture the die, and wasting it would be a significant loss of resources. However, when the die doesn't achieve satisfactory yield on the Intel 3 production line, the company would usually discard it if it can't extract a reasonable number of working cores. Amidst one of the highest-ever recorded CPU shortages, Intel is doing the opposite. The company is using these defective or scrap dies and packaging them into lower-class SKUs to sell to its customers, as any CPU availability is crucial, and customers are eagerly purchasing them. Imagine a wafer edge, which is round, having only a few working P-Cores, and that being packaged into a CPU that a hyperscaler would integrate into their offering.