TSMC has decided not to use High-NA EUV lithography for its upcoming angstrom-era A14 node. Instead, the world's largest contract chipmaker will stick with the field-proven 0.33-NA EUV tools. Senior Vice President at TSMC, Kevin Zhang, explained that the choice reflects TSMC's ongoing focus on keeping manufacturing steps straightforward and costs under control. Zhang noted that volume production of A14 chips is slated to begin in 2028, and the company believes it can hit its performance, yield, and density targets all the way through the two-nanometer generation without the need for High-NA equipment. He pointed out that by limiting the number of mask layers from one generation to the next, TSMC can offer customers more affordable solutions without sacrificing complexity where it counts.

This strategy places TSMC in step with Intel Foundry and several DRAM producers, who have already adopted High-NA selectively for their most critical layers. High-NA EUV scanners come with a steep sticker price of $380 million, and they require higher exposure doses and tend to run at lower throughput than standard tools. IBM researchers recently confirmed that a single High-NA exposure can cost up to 2.5 times more than a low-NA shot. Yet, when you compare a four-mask low-NA flow to a single High-NA pass, total wafer costs can drop by roughly 1.7 to 2.1 times. Despite those savings in complex multi-patterning scenarios, analysts at SemiAnalysis still expect full cost parity won't arrive until around 2030. So far, Intel is the only major foundry committed to High-NA for high-volume production. It has already processed over 30,000 trial wafers on its 14A node using ASML's Twinscan EXE:5000 High-NA tool.