Thursday, May 15th 2025
Intel Forecasts Foundry Break-Even in 2027 as 14A Node Debuts
Intel says its struggling Foundry division will finally break even in 2027, just as its advanced 14A process comes online. The announcement came during the J.P. Morgan Global Technology, Media & Communications Conference, where CFO David Zinsner outlined the plan to offset years of quarterly losses. Intel has been pouring billions of dollars into new fabs and equipment as it races to keep pace with TSMC and Samsung. Its first milestone is the 18A process, whose first product, codenamed Panther Lake, will arrive in client PCs late in 2025, with volume production following in 2026. Intel also plans to use 18A for its next Xeon "Clearwater Forest" server chips and offer it to a small set of external partners to prove the technology's readiness. "We have to start by using our own chips," Zinsner explained. "Once we show that Panther Lake and Clearwater Forest perform as expected, we'll see more interest from outside customers for 18A, 18A-P, and then 14A."
He acknowledged that initial adoption is low, but expressed confidence that proven performance will drive committed volume. A key part of the strategy is the use of High-NA EUV lithography at 14A. Zinsner admitted this will raise equipment costs at first, but he believes the improved transistor density and power efficiency will more than make up for the investment, boosting margins and factory utilization. Intel's path to break even also incorporates revenue from mature nodes such as Intel 16/12, advanced packaging services, and collaborations with UMC and Tower. Under its "smart capital" model, the company will balance internal wafer demand with third-party work, maintaining flexibility and cost discipline. With a relatively modest external revenue target (for a cash-bleeding foundry), low to mid single-digit billions per year, Intel Foundry aims to reach break-even in 2027 and move into sustained profitability soon afterward. By 2027, Intel 14A node and ehnaced the 1.8 nm-class 18A-P(T) node will also complement these break-even efforts.
Source:
via Tom's Hardware
He acknowledged that initial adoption is low, but expressed confidence that proven performance will drive committed volume. A key part of the strategy is the use of High-NA EUV lithography at 14A. Zinsner admitted this will raise equipment costs at first, but he believes the improved transistor density and power efficiency will more than make up for the investment, boosting margins and factory utilization. Intel's path to break even also incorporates revenue from mature nodes such as Intel 16/12, advanced packaging services, and collaborations with UMC and Tower. Under its "smart capital" model, the company will balance internal wafer demand with third-party work, maintaining flexibility and cost discipline. With a relatively modest external revenue target (for a cash-bleeding foundry), low to mid single-digit billions per year, Intel Foundry aims to reach break-even in 2027 and move into sustained profitability soon afterward. By 2027, Intel 14A node and ehnaced the 1.8 nm-class 18A-P(T) node will also complement these break-even efforts.
21 Comments on Intel Forecasts Foundry Break-Even in 2027 as 14A Node Debuts
If they don't have enough volume for their own chips, how on earth they would produce more chips for other companies?
It's not the case that they have magically acquired dozens of High-NA EUV machines in recent months. ASML can deliver roughly 5-6 of those annually. Even if Intel hypothetically buys all, which is of course not the case as TSMC and Micron have them delivered already, how much time will pass until Intel have enough of those delivered and assembled for volume production? A reminder, they assembled only two by October 2024. Now, this might be three only.
www.electronicsweekly.com/news/business/intel-sets-up-second-high-na-euv-machine-2024-10/
Ever heard about ramping of production?
Let s wait and see. ArrowLake was not good.
Lunar lake was good for its intended target.
Let see how panther lake is ending up being, and then we can complain (or not)!
We dont have so long to wait anyway.
It's hard not to be skeptical of Intel PR when it turned out to be hollow promises so many times before.
They should get their Arc GPU's into the AI game.... that might be big for them?
They also had smaller datacenter AI accelerators code-named Arctic Sound but that project didn't turn out well and the Intel Data Center GPU Flex series is based on desktop Arc dies instead. They also planned a successor called Lancaster Sound which got cancelled.
The last product is Gaudi AI chips from their Habana Labs acquisition which aren't popular either.
So you can't say that Intel didn't try, but in the end didn't score a big win with AI.
But Arrow Lake was originally promised for the Intel 20A node, which casts doubt over Panther Lake. Still, with Arrow Lake Intel sort of stopped talking about and being vague when mentioning it, whereas Intel is regularly insisting that Panther Lake or some client CPU is coming to 18A this year.
We are analysing the situation and we need to be honest, including you.
Ramping up one thing, and ramping up on good, competitive and ready process nodes is another.
Years of delay on 10nm and then smaller nodes cost them dearly. That's why they were forced to use TSMC, to stay competitive.
They ramped up Intel 3 for entire data center. Still, it's not enough to ramp up. Zen5 EPYCs are up to 40% faster. Intel appears to be almost two generations behind with Xeons right now. How are you going to excuse that?
www.servethehome.com/welcome-back-intel-xeon-6900p-reasserts-intel-server-leadership/5/
So far, so good. Only two years behind, aka one generation. Now, devil is always in detail. What does it take for Granite Rapids to compete with Zen4 Genoa? Let's find out.
1. Single 9680P is 37% faster, on average, than single EPYC 9654, but... per core Xeon scores 6.50 and EPYC scores 6.34 points. Xeon is also almost three times more expensive (!), uses 25% more power and faster RAM. How does it look like now to you?
2. How many cores does Xeon 6980P 2P system need to achieve the parity with Zen4 EPYC 9684X 2P system? It takes 256 Xeon cores and 192 EPYC cores. The same performance, on average, with 33% more cores, 20% more power and 20% more expensive.
With CPUs, especially server chios, you need to take into account more factors, such as performance per core, per Watt, cost of rack ownership, etc.
That's why I said that current Xeons are almost two generations behind. Would you agree?
2. Regarding the comparison with the Epyc 9684X, Phoronix did benchmark both in a 2P system. In the "Geometric Mean" result the Xeon was 11.8% faster. Now 33% more cores ought to be more than 11.8% faster in multithreaded tests, but the Phoronix tests included lightly threaded tests and some outliers that suggest an optimization problem (testing a 1-year old series against a new release at the time). Moreover as a task scales up to more threads, the data synchronization overhead increases so it's reasonable to expect performance not to scale perfectly for a single task. Lastly, the Xeon did win in the less threaded workloads as well. www.phoronix.com/review/intel-xeon-6980p-performance/11
So no. I don't think Xeon is 2 generations behind. It was released after Zen 4 and just before Zen 5 Epyc and it performs between Zen 4 and Zen 5. Since the performance leans closer to Zen 4 and the timing closer to the of release closer to Zen 5, I'd put Xeon around 0.7 generations behind.
Edit: regarding the chart you showed, it comes from this Phoronix article, and it's inconsistent with Phoronix's test result of the same CPUs in the article I shared.
www.phoronix.com/review/amd-epyc-9965-9755-benchmarks/14
Since the early 1980s, most electronics have relied on the use of complementary metal–oxide–semiconductor (CMOS) transistors.
However, the principles of CMOS operation, involving a switchable semiconductor conductance controlled by an insulating gate, have remained largely unchanged, even as transistors are miniaturized to sizes of 10 nanometres.
We investigated what dimensionally scalable logic technology beyond CMOS could provide improvements in efficiency and performance for von Neumann architectures and enable growth in emerging computing such as artifical intelligence. Such a computing technology needs to allow progressive miniaturization, reduce switching energy, improve device interconnection and provide a complete logic and memory family.
Here we propose a scalable spintronic logic device that operates via spin–orbit transduction (the coupling of an electron’s angular momentum with its linear momentum) combined with magnetoelectric switching.
The device uses advanced quantum materials, especially correlated oxides and topological states of matter, for collective switching and detection.
We describe progress in magnetoelectric switching and spin–orbit detection of state, and show that in comparison with CMOS technology our device has superior switching energy (by a factor of 10 to 30), lower switching voltage (by a factor of 5) and enhanced logic density (by a factor of 5). In addition, its non-volatility enables ultralow standby power, which is critical to modern computing.
The properties of our device indicate that the proposed technology could enable the development of multi-generational computing.
So today is the year 2025 - Where is MESO (magneto electric spin orbit) and everything they promised?????
Something that isn't reflected in general benchmarks?
I know what i would be putting my money towards for that server.
Edit: Certainly great mail server performance is part of Intel's plan to win sales. But I think it's a part of the plan, and not the central point of Granite Rapids.
*Mail server here being a metaphor for the tasks Granite Rapids has dedicated instructions for.