Monday, June 16th 2025
Intel "Nova Lake-S" Series: Seven SKUs, Up to 52 Cores and 150 W TDP
Rumors of Intel's "Nova Lake-S" processors are increasing, meaning that the design is nearing completion. Expected to arrive in the second half of 2026, Nova Lake-S will offer configurations ranging from mainstream quad-core models to a flagship with 52 cores. Initial information suggests that Intel will employ a tile-based design, separating LPE cores from P-Cores and E-Cores to optimize flexibility and yield. At the top of the lineup is the rumored Core Ultra 9 model, possibly designated 385K. It will combine 16 P-cores, 32 E-cores, and four LPE-cores for a total of 52 cores, as previously rumored. With a TDP of 150 W, it will be the most powerful SKU Intel prepared for this generation. Below the flagship, Intel appears to be planning a Core Ultra 7 SKU with 14 P-cores, 24 E-cores, and four LPE cores, totaling 42 cores.
The Core Ultra 5 series may include three variants: a 28-core version with eight P-cores, 16 E-cores, and four LPE-cores; a 24-core version with eight P-cores, 12 E-cores, and four LPE-cores; and an 18-core model with six P-cores, eight E-cores, and four LPE-cores. Entry-level Core Ultra 3 parts would feature either a 16-core configuration with four P-cores, eight E-cores, and four LPE-cores, or a 12-core option with four P-cores, four E-cores, and four LPE-cores, both targeting a 65 W power envelope. All desktop SKUs are expected to feature four LPE cores on a separate die, suggesting a multi-tile package similar to Meteor Lake. Power demands will range from 65 W in entry-level segments to 150 W for high-end parts. Intel is reportedly preparing a new LGA 1954 socket even as it readies an Arrow Lake-S refresh for late 2025. Intel has also reportedly designated Xe3 "Celestial" for graphics rendering and Xe4 "Druid" for media and display duties.
Sources:
chi11eddog on X, via VideoCardz
The Core Ultra 5 series may include three variants: a 28-core version with eight P-cores, 16 E-cores, and four LPE-cores; a 24-core version with eight P-cores, 12 E-cores, and four LPE-cores; and an 18-core model with six P-cores, eight E-cores, and four LPE-cores. Entry-level Core Ultra 3 parts would feature either a 16-core configuration with four P-cores, eight E-cores, and four LPE-cores, or a 12-core option with four P-cores, four E-cores, and four LPE-cores, both targeting a 65 W power envelope. All desktop SKUs are expected to feature four LPE cores on a separate die, suggesting a multi-tile package similar to Meteor Lake. Power demands will range from 65 W in entry-level segments to 150 W for high-end parts. Intel is reportedly preparing a new LGA 1954 socket even as it readies an Arrow Lake-S refresh for late 2025. Intel has also reportedly designated Xe3 "Celestial" for graphics rendering and Xe4 "Druid" for media and display duties.
104 Comments on Intel "Nova Lake-S" Series: Seven SKUs, Up to 52 Cores and 150 W TDP
The rumored Novalake MT uplift is quite interesting comparing 8P16E NVL vs 8P16E ARL by MLID. 23% when ST gain of P core is 10% sounds like most, or at least half the gains are from P core. Considering E core is expanding to accomodate AVX512 and thus general improvements in FP IPC at the least, yet only at most 10% gain can be attributed to them, is either suspect or pitful, especially considering it doesn't make sense to expect clock regression like Arrowlake. Heck, current gains of Darkmont before it are of the same magnitude. Doesn't look good for a team that supposedly takes over from P core team in the future. Then again, Zen5 vs Zen4 was similar.
I wonder if P core sharing L2 was borrowed from Gracemont back then seeing the results and arrangement being similar to Crestmont cluster. On one hand, in MT loads, the P core will have 1MB less cache per P core to work with on average, however, the design would not only have far less die space per P core than before so core to core latencies may possibly be offset, could possibly be a net gain in performance and efficiency since less time and power is spent on the ring bus. In fact, core to core latency may be reduced by a lot looking at Arrowlake. i9 285K from launch had way better E core to core and even across clusters' latencies than between the P cores. Within an E core cluster, E cores got down to half the latency vs P cores. Obviously the cache setup will play a part, however consider that even then, P core cluster will have twice the L2 per core than E core, while only currently being about 20%+- faster overall.
chipsandcheese.com/p/examining-intels-arrow-lake-at-the
The larger L3 may deal with latency and/or cost issues normally, but I believe they may be less than what people expect due to one thing. The P cores are now clustered. I believe the number of ring stops will reduce to 8 from 12, as the P cores are now clustered in 2, and E core clusters share L3 cache as well, so why wouldn't the P cores too, So the slices just get larger, from 3MB to 16MB, or maybe 2 slices cache to 1 stop? Don't know if it's possible or optimal vs space used but bandwidth gaine. It could be possible that Novalake retains Arrowlake memory latencies overall, but with higher hit rate. If true, then I guess good job Intel. However, all that cache brings 3% gains over non BLLC in ST (but not gaming)? Tough but we'll see. Even tougher are the quoted 12% gains in MT over non BLLC. But what I can be sure of, is people overclocking the cache to eek out performance as I am sure it will operate at lower speeds to save power and for yield.
RAM side latencies may be a wash (at least in its effect. The IMC is much better, so even if larger banks with worse latency are used for L3, the RAM latency could be better hidden by both the drastically higher hit rate of L3 (and fewer ring stops) and the much better bandwidth. At least later on when RAM kits get better. There may be a net improvement in overall latencies.
I would normally expect clock targets to be 5.7ghz to 6ghz. I am hearing crazy numbers about AMD though, but I kind of doubt they would achieve 50% higher core count per CCD and drastically leave Intel in the dust with clocks at the same time while both use N2P. However 16% non BLLC uplift implies a 5% clock speed boost and 10% IPC gain or just IPC gain at similar clocks. Maybe AMD gets 6.2ghz and 12% IPC vs 6ghz and 10% IPC from Intel or some such. The only potentially significant clock difference should be on X3D vs BLLC imo
Final thing, 1 Arctic wolf cluster is used as LPE cores but again away from compute tile unlike Lunarlake but more like Arrowlake. I wonder how that affects (if any) ring clocks, latencies, etc when inevitably, workloads are offloaded there. Unlike Arrowlake//Meteorlake with its anaemic 2 core cluster of crestmont, Novalake should be well north of 2-4X performance of the LPE so less workloads should be handed back to compute tile, which could lower overall power consumption, but mostly by expanding what is considered "idle" tasks (Intel showed of Lunarlake LPE running Microsoft teams without offloading to the P cores) yet that means that FMAX clocks won't improve because of this lower consumption.
Releasing the 1 tile first I guess will help them find optimal pricing for the 2 tile behemoth after gauging both reception of the 1 tile SKU, and AMD's response (maybe they will release X3D day one?)
My belief is that it will be rather slow, maybe at best zen 4/zen 5 mobile level, maybe better, but more likely worse.
As for transistor budget, Gracemont and Skymont both got quite beefy upgrades internally. They especially emphasized the expansions in their vector engines and supporting structures. Even with what they have, my guess is expanding L1 data cache to cover 4 from 3 128 bit vector lanes at a time (they have 4 lanes, but the cache can't handle all 4 yet) and a few changes could give AVX512 support.
Alternatively, since its already 4 128 bit, then why not make them 2 256 bit? Whatever the case may be, I think they are already 75% there in terms of resources to have at least basic support.
At the end of the day I am not a chip designer and am still learning how these things work CPU side.