"Bartlett Lake-S" is an interesting chip by Intel, given that its "Nova Lake-S" desktop processors with large L3 caches won't arrive before mid/late 2026. The chip is built on the idea that the "Raptor Cove" P-core offers gaming performance comparable or better to the "Lion Cove" P-cores implemented on "Arrow Lake-S." Intel figured that for a monolithic silicon with a similar die-size of "Raptor Lake-S," which has 8 P-cores and 4 E-core clusters, it could design a silicon with 12 P-cores for the same number of ring-stops, sharing the same 36 MB of L3 cache. A recent post on Twitter by Jaykihn highlights the stepping of this silicon as A0, but there's more to the story—apparently Intel will recycle its older "Raptor Lake" and "Alder Lake" silicon within "Bartlett Lake" generation, and refer to them as "Bartlett Lake Hybrid."

This "Bartlett Lake Hybrid" line of processors will reuse B0, C0, and H0 chips. The B0 chip is the original "Raptor Lake-S," which comes with an 8P+16E core-configuration, 36 MB of L3 cache, 2 MB of L2 cache per P-core, and 4 MB of L2 cache per E-core cluster. The C0 silicon is derived from "Alder Lake-S," with an 8P+8E config that has 1.25 MB of L2 cache per P-core and 2 MB of L2 cache per E-core cluster, with 30 MB of L3 cache. The H0 silicon originally drove the lower half of the 12th Gen Core family, it has 6 P-cores, each with 1.25 MB of L2 cache, no E-core clusters, and 18 MB of L3 cache.Intel will not market "Bartlett Lake-S" as the 15th Gen Core series, but switch to its new nomenclature under the Core 2-series, but without the "Ultra" brand extension, denoting the lack of an on-die NPU. Unfortunately, leaked marketing material by Intel points to the chip being primarily targeted at the OEM and embedded markets, and not DIY retail, in other words, there are no signs yet of a retail desktop chip that you can pop into a Socket LGA1700 rig.

"Bartlett Lake-S" A0 will be the desktop processor with the highest P-core count from Intel, and will also be the processor with the highest P-cores within a single compute complex (i.e. sharing an L3 cache), across brands, because the 12-core and 16-core AMD Ryzen desktop processors have their cores split between two complexes, in the form of two CCDs. When threads migrate between CCDs, their working data must be transferred via the I/O die. If the data still resides in the source CCD's cache, it is duplicated into the destination CCD's L3, otherwise, it must be fetched from DRAM.