Monday, April 20th 2026

SK hynix Begins Mass Production of 192GB SOCAMM2

SK hynix Inc. (or "the company", www.skhynix.com) announced today that it has begun mass production of the 192 GB SOCAMM2, a next-generation memory module standard based on the 1cnm process (sixth-generation of the 10-nanometer technology) LPDDR5X low-power DRAM.

SOCAMM2 is a module that adapts low-power memory - which was previously used mainly in mobile products like smartphones - for server environments. It is designed to be a primary memory solution for next-generation AI servers.
SK hynix emphasized that the 1cnm based SOCAMM2 product that is now in mass production delivers more than double the bandwidth with over 75% improved power efficiency compared to conventional RDIMM, providing an optimized solution for high performance AI operations.

In particular, the company noted that its SOCAMM2 products are designed for NVIDIA Vera Rubin platform.

SK hynix expects the new SOCAMM2 product will fundamentally resolve the memory bottlenecks encountered during the training and inference of large language model (LLM) with hundreds of billions of parameters, thereby playing a pivotal role in dramatically accelerating the processing speed of the overall system.

The company stated that with the AI market shifting focus from inference to training, SOCAMM2 is gaining significant attention as a next-generation memory solution capable of operating LLMs with low power consumption. To meet the demands of its global Cloud Service Provider (CSP) customers, SK hynix has not only been providing a supply portfolio, but also stabilized its mass production system early on.

"By supplying the 192 GB SOCAMM2, SK hynix has established a new standard for AI memory performance," Justin Kim, President & Head of AI Infra (CMO, Chief Marketing Officer) at SK hynix said. "We will solidify our position as the most trusted AI memory solution provider, through close collaboration with our global AI customers."

Source: SK hynix
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14 Comments on SK hynix Begins Mass Production of 192GB SOCAMM2

#2
Mysteoa
Wondering if and which of these new RAM form factors will become available for consumer desktop PC.
Posted on Reply
#3
Ihnako
WonkoTheSaneUKSo... AI next take phone memory?
If I remember correctly, it already has.

Using LPDDR5X instead of regular DDR5 makes sense in many ways, especially regarding power consumption and heat generation.
Sure, instead of scrificing it to our AI overlord it could be better used in real-world scenarios in the field like notebooks, tablets, smartphones etc.
Posted on Reply
#4
bonehead123
Sooooo....

In other words (without all the techno-babble)........

more unobtainium (at least for us little people), thanks to, well you guessed it, A.friggin.I :(
Posted on Reply
#5
_roman_
Anything which seems not be soldered DRAM to a motherboard with cpu is positive.

The dram technology depends on the memory controller regardless of the cpu or motherboard in question. no one prevents amd to allow low power ddr5 on consumer motherboards with all the issues and flaws.
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#6
Intelko
MysteoaWondering if and which of these new RAM form factors will become available for consumer desktop PC.
I think - Yes.
The answer.
Posted on Reply
#8
chrcoluk
Why are they making this when they cant make enough consumer DIMMs?
Posted on Reply
#9
igormp
WonkoTheSaneUKSo... AI next take phone memory?
Systems like Nvidia's Grace/Vera were already using LPDDR memory, they are only making it socketed instead of soldered now.
chrcolukWhy are they making this when they cant make enough consumer DIMMs?
This is not really target to consumers at this moment, and the main issue with availability were with the memory IC modules, not the PCBs those went to.
So, instead of selling Nvidia a bunch of bare LPDDR ICs, they'll solder those into that SOCAMM2 PCB and sell it to Nvidia or any other OEM.
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#10
thestryker6
What I'm finding interesting is the increased density available on these enterprise packages. They seem to be using very high density components compared to client. The 16GB 32-bit packages used for laptops and whatnot are made up of 4Gb die whereas these SOCAMM2 modules are using 24Gb die to make 48GB 16-bit packages. While we're probably never going to see it now, with the memory apocalypse and LPDDR6 coming, it seems like there ought to be some room for improvement on client density.
Posted on Reply
#11
Wirko
thestryker6What I'm finding interesting is the increased density available on these enterprise packages. They seem to be using very high density components compared to client. The 16GB 32-bit packages used for laptops and whatnot are made up of 4Gb die whereas these SOCAMM2 modules are using 24Gb die to make 48GB 16-bit packages. While we're probably never going to see it now, with the memory apocalypse and LPDDR6 coming, it seems like there ought to be some room for improvement on client density.
Yes, these modules are designed to be dense, liquid-coolable and expensive, far removed from consumer tech. They use 16-high TSV stacks of 3 GB dies, equalling HBM3e and HBM4 (or variants thereof, because both have multiple variants of die capacity and stack height). Wire bonding can't be used to make these tall stacks (as Goog AI tells me), leaving costly TSV as the only option.
However, one chip package is 32 bits wide, not 16, because a SOCAMM is 128 bits wide.
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#12
thestryker6
WirkoHowever, one chip package is 32 bits wide, not 16, because a SOCAMM is 128 bits wide.
They're only using 16 die worth of capacity so that means something else has also changed with the packaging then since die are typically 1-bit.
Posted on Reply
#13
Wirko
thestryker6They're only using 16 die worth of capacity so that means something else has also changed with the packaging then since die are typically 1-bit.
What do you mean, 1-bit? Most common DDR dies have an 8-bit data bus and aren't stacked (but some are 16-bit so only 4 sit on a DIMM). GDDR and LPDDR dies are 32-bit, and LPDDR stacks too. HBM dies are 128-bit I believe, but stacks combine the bits/wires of all dies to make a 1024- or 2048-bit data bus. Finally, NAND dies have an 8-bit data bus (one channel), and a stack of 4 or 8 or 16 dies must have 32 bits for example, if the SSD is made up of a single chip package and a 4-channel controller.
Posted on Reply
#14
thestryker6
WirkoWhat do you mean, 1-bit? Most common DDR dies have an 8-bit data bus and aren't stacked (but some are 16-bit so only 4 sit on a DIMM). GDDR and LPDDR dies are 32-bit, and LPDDR stacks too. HBM dies are 128-bit I believe, but stacks combine the bits/wires of all dies to make a 1024- or 2048-bit data bus. Finally, NAND dies have an 8-bit data bus (one channel), and a stack of 4 or 8 or 16 dies must have 32 bits for example, if the SSD is made up of a single chip package and a 4-channel controller.
So this was just a fundamental misunderstanding on my part regarding LPDDR5/5X (it took a while to hunt down actual diagrams so I could figure out where I might have gone wrong):

LPDDR5/5X has an array configuration which covers the entire package, but this doesn't correlate to the die being used to make up the package. So 16GB 32-bit LPDDR5X is has a 4Gx32 configuration, but it uses 8x 2Gx8 die in a dual channel dual rank configuration to make up that package. This is where my mistake happened because I assumed it was like DDR5 where the configuration directly relates to the die being used.
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