Wednesday, May 13th 2026

Apple Taps Intel 18A-P Node for M7 MacBook Chip, 14A Node for iPhone

According to the sell-side equity research firm GF Securities, Apple is set to utilize both Intel's 18A-P and 14A nodes for its product lineups. As previously reported, the company will employ Intel's advanced 18A-P node for the M7 SoCs that power MacBook Air and entry-level MacBook Pro laptops. Intel's investment in the development and manufacturing ramp of the 14A node will also be beneficial, as Apple plans to use the 14A node for producing A21 SoCs for iPhones. The 18A-P node is ideal for Apple's laptop SoCs, providing a balance between efficiency and speed. It offers a 9% performance increase at the same power level or achieves 18% power savings at the same performance level compared to the standard 18A node, resulting in laptops with good frequency and low power usage. With Apple moving away from TSMC's 3 nm node in the current M5 SoC, the improvements will be significant and are expected to be realized by 2027.

For the A21 iPhone SoCs, Apple will use Intel's advanced 14A node, which promises a generational leap in density, frequency, and power savings. Apple's primary goal is to employ a more advanced node for mobile devices, with plans to have these chips ready by 2028. As this is anticipated to begin in about two years, Apple will likely wait for the final 14A PDK before starting trial production. It remains uncertain whether the company will manufacture its A21 Pro SoC at TSMC and leave the regular version to Intel. However, Apple is gradually diversifying its supply chain with more silicon manufacturers. With advanced packaging, Intel can compete with TSMC in many areas, and we are eager to see the outcomes of this competition.

Finally, Apple's solutions might require some packaging techniques to meet the expected performance of the M7 SoC. This could involve a combination of the Foveros family, including Foveros-S, R, B, or Foveros Direct, paired with EMIB. These options offer interposers and RDL options, along with true 3D stacking using Cu-to-Cu hybrid bonding, for scenarios that demand extreme die-to-die bandwidth or power efficiency. Additionally, small silicon EMIB bridges are available in variants like EMIB-M, with embedded MIM capacitors, and EMIB-T, with TSVs.
Source: via Juakn05 on X
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19 Comments on Apple Taps Intel 18A-P Node for M7 MacBook Chip, 14A Node for iPhone

#1
LastDudeALive
Apparently stating the obvious reason why this is happening isn't allowed here, even if the article itself mentions it, so I'll just say congratulations to Intel for catching up on fab tech.
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#2
kondamin
We're at m5 now, 6 should launch later this year.
18 months to design and test a new chip at a new foundry partner???
Not holding my breath
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#3
darakian
I wonder if this will be a second source type deal where they mix tsmc and intel chips or if it's exclusive. I could see either being plausible tbh
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#4
Nhonho
I would never hand over the design of a "state-of-the-art" chip to Intel.
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#5
Wirko
darakianI wonder if this will be a second source type deal where they mix tsmc and intel chips or if it's exclusive. I could see either being plausible tbh
Having two foundries making the same chip would be very costly. Many phases of design and then the entire verification, photomask production, test production, testing and whatnot would have to be repeated two times. If this is what you mean by "second source", it's very unlikely.
(Although Goog AI tells me that Qualcomm does that routinely. Didn't check further.)
Posted on Reply
#6
lemonadesoda
WirkoHaving two foundries making the same chip would be very costly. Many phases of design and then the entire verification, photomask production, test production, testing and whatnot would have to be repeated two times. If this is what you mean by "second source", it's very unlikely.
(Although Goog AI tells me that Qualcomm does that routinely. Didn't check further.)
I think for the sheer scale of chips we are talking about here, the QA phase is a relatively small cost, and irrelevant if a $ value is put on supply chain security.
Posted on Reply
#7
Unregistered
Yeah, buhhhhtttt 20A was a failure, so Intel is a failure...
Posted on Edit | Reply
#8
Eliad Buchnik
WirkoHaving two foundries making the same chip would be very costly. Many phases of design and then the entire verification, photomask production, test production, testing and whatnot would have to be repeated two times. If this is what you mean by "second source", it's very unlikely.
(Although Goog AI tells me that Qualcomm does that routinely. Didn't check further.)
Depends on scale, for an Apple SOC that sells in the tens or hundreds of millions, it's not that costly. They actually did it with A9 and used both Samsung 14LPE and TSMC 16FFC, there was big story back then that iPhone using the TSMC made SoC, had significantly better battery life under continuous heavy CPU workloads (for typical usage it was similar enough). Since then they only sourced from TSMC, but due to current conditions I can see them dual sourcing again to ensure supply.
Posted on Reply
#9
darakian
WirkoHaving two foundries making the same chip would be very costly. Many phases of design and then the entire verification, photomask production, test production, testing and whatnot would have to be repeated two times. If this is what you mean by "second source", it's very unlikely.
(Although Goog AI tells me that Qualcomm does that routinely. Didn't check further.)
For sure it's expensive, but apple's done it before with the a9 which was split across samsung and tsmc. Intel has reportedly moved to industry standard design tools so maybe it's something they could stomach and maybe they even use it as price pressure. I'm not saying it will happen for sure, but I could see it.
Posted on Reply
#10
L'Eliminateur
kondaminWe're at m5 now, 6 should launch later this year.
18 months to design and test a new chip at a new foundry partner???
Not holding my breath
you do know that silicon development takes YEARS(and i'm not talking 2), right?, if you don't now you know, a cpu with a new uarch you see "launched" today has been in development from when the 2 previous microarch have come out, for example you did know that ZEN5 started development before/at the time ZEN3 came out

so 18 months is nothing, in fact what you see about 18 months is because everything about the M7 is already finalized and the only thing left is the layout and porting to a particular foundry PDK, and that M7 SoC has been in development(and possibly finished in development and features) at least 2+ years ago, possibly when M3 or M4 came out
Posted on Reply
#11
kondamin
L'Eliminateuryou do know that silicon development takes YEARS(and i'm not talking 2), right?, if you don't now you know, a cpu with a new uarch you see "launched" today has been in development from when the 2 previous microarch have come out, for example you did know that ZEN5 started development before/at the time ZEN3 came out

so 18 months is nothing, in fact what you see about 18 months is because everything about the M7 is already finalized and the only thing left is the layout and porting to a particular foundry PDK, and that M7 SoC has been in development(and possibly finished in development and features) at least 2+ years ago, possibly when M3 or M4 came out
sure, doesn’t make adjusting the design to the node easy and fast for the people that are only starting making chips for other firms than intel,it self
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#12
Nhonho
L'Eliminateuryou do know that silicon development takes YEARS(and i'm not talking 2), right?, if you don't now you know, a cpu with a new uarch you see "launched" today has been in development from when the 2 previous microarch have come out, for example you did know that ZEN5 started development before/at the time ZEN3 came out
Today, all development of new chips is greatly accelerated by AI.

A completely new architecture, like the 1st ZEN architecture of the 1st generation Ryzen, took about 5 years to be develop. Subsequent ZEN architectures, which are based on the 1st ZEN generation, took much less time to completed.

TODAY, all chip designers use enormous AI data centers for both chip design and debugging fases, which drastically reduce all the chip development time. Today, with AI-assisted development, it's possible to complete a CPU modification, that used to take several months, in just a few days or in a week.

When a third party, like Apple, provides Intel with a "state-of-the-art" chip design for Intel to manufacture them, I think Intel will undoubtedly use that design to feed its database (of Intel's DC) in order to Intel develop its own future chips. Intel won't make an exact copy of third-party designs, but it will use projects done by third parties to feed and improve its own AI data center database.
Posted on Reply
#13
kondamin
NhonhoToday, all development of new chips is greatly accelerated by AI.

A completely new architecture, like the 1st ZEN architecture of the 1st generation Ryzen, took about 5 years to be develop. Subsequent ZEN architectures, which are based on the 1st ZEN generation, took much less time to completed.

TODAY, all chip designers use enormous AI data centers for both chip design and debugging fases, which drastically reduce all the chip development time. Today, with AI-assisted development, it's possible to complete a CPU modification, that used to take several months, in just a few days or in a week.

When a third party, like Apple, provides Intel with a "state-of-the-art" chip design for Intel to manufacture them, I think Intel will undoubtedly use that design to feed its database (of Intel's DC) in order to Intel develop its own future chips. Intel won't make an exact copy of third-party designs, but it will use projects done by third parties to feed and improve its own AI data center database.
ML has been used for well over a decade, even amd's bulldozer was made with that approach
Posted on Reply
#14
L'Eliminateur
NhonhoToday, all development of new chips is greatly accelerated by AI.

A completely new architecture, like the 1st ZEN architecture of the 1st generation Ryzen, took about 5 years to be develop. Subsequent ZEN architectures, which are based on the 1st ZEN generation, took much less time to completed.

TODAY, all chip designers use enormous AI data centers for both chip design and debugging fases, which drastically reduce all the chip development time. Today, with AI-assisted development, it's possible to complete a CPU modification, that used to take several months, in just a few days or in a week.

When a third party, like Apple, provides Intel with a "state-of-the-art" chip design for Intel to manufacture them, I think Intel will undoubtedly use that design to feed its database (of Intel's DC) in order to Intel develop its own future chips. Intel won't make an exact copy of third-party designs, but it will use projects done by third parties to feed and improve its own AI data center database.
where did you pull that info from, it's not true at all, it's not accelerated by AI at all, none of the chip design tools use AI. And all zen architectures took years to develop even being derived from zen (and you don't derive all of them from zen, zen6 is a huge departure)

so no, none of the tools can complete a cpu modification in the time you say
Posted on Reply
#15
Unregistered
kondaminML has been used for well over a decade, even amd's bulldozer was made with that approach
Yeah, and that turned out to be soooo wonderful... 😒
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#16
Dr. Dro
NhonhoI would never hand over the design of a "state-of-the-art" chip to Intel.
You seem to imply that Intel doesn't have state of the art processors themselves... besides, this is IFS. Separate entity.
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#17
Nhonho
Dr. DroYou seem to imply that Intel doesn't have state of the art processors themselves
You misunderstood, again. A "state-of-the-art chip design" means a very well-made design of a new and highly complex chip.
L'Eliminateurwhere did you pull that info from, it's not true at all, it's not accelerated by AI at all, none of the chip design tools use AI. And all zen architectures took years to develop even being derived from zen (and you don't derive all of them from zen, zen6 is a huge departure)

so no, none of the tools can complete a cpu modification in the time you say
Ah, OK... I was just thinking that we're in 2026, not the early 90s.

And the engineers at Intel, AMD, Nvidia, and other major chip developers are incredibly stupid; they still haven't realized that AI can drastically accelerate chip design and also significantly shorten the debugging phase.

Get on a plane and go teach them that they can use AI for all of this. Your knowledge is sorely lacking among the engineers at those companies.
Posted on Reply
#18
Dr. Dro
NhonhoYou misunderstood, again. A "state-of-the-art chip design" means a very well-made design of a new and highly complex chip.
...you mean like Intel's processors? Have you looked at NVL?
Posted on Reply
#19
L'Eliminateur
NhonhoYou misunderstood, again. A "state-of-the-art chip design" means a very well-made design of a new and highly complex chip.



Ah, OK... I was just thinking that we're in 2026, not the early 90s.

And the engineers at Intel, AMD, Nvidia, and other major chip developers are incredibly stupid; they still haven't realized that AI can drastically accelerate chip design and also significantly shorten the debugging phase.

Get on a plane and go teach them that they can use AI for all of this. Your knowledge is sorely lacking among the engineers at those companies.
i ask you again,w hat are your sourced that theyr'e using AI?, please link me cadence press releases/datasheets showing exactly that and in what quality are they used.

Stop thinking that "AI accelerates everything" because it's plain bullshit

So no, AI doesn't "drastically accelerate" diddly-squat in chip design
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