Qualcomm has officially validated its High Bandwidth Compute (HBC) concept, which the company showcased this summer. Instead of using traditional HBM and compute dies, Qualcomm has developed a technology that stacks multiple LPDDR layers and embeds a base die that serves as a compute engine for AI inference. In Qualcomm's San Diego lab, the first-generation HBC has achieved silicon validation with full read-write and near-memory computation capabilities. HBC utilizes LPDDR memory, stacking it across multiple layers in a 3D vertical space and interconnecting them with through-silicon vias (TSVs). This approach provides better energy efficiency than traditional HBM, which stacks regular DDR in vertical layers, as the low-power DDR (LPDDR) chips consume less power while delivering similar bandwidth and capacity.

Qualcomm has successfully stacked multiple LPDDR layers on top of each other, with the base of the HBC being a compute die that performs near-memory computation and offloads processing to near-memory dies. This technique is similar to what HBM4 memory currently does, with the base die being a logic die to better integrate compute solutions for packet tracing and data preparation for entering and exiting HBM. However, Qualcomm aims to achieve higher efficiency and more optimized data movement, with a 6x increase in bandwidth per watt compared to the current HBM specification. The goal is to have compute directly under these memory stacks so that data travels only a few microns instead of a few centimeters.HBC Gen 1 achieved 133 TB/s of total memory bandwidth on the AI250 accelerator card, an 18x increase over the LPDDR5X currently used in the AI200 card from Qualcomm. This is a total accelerator memory bandwidth number, not a per-HBC module bandwidth. The company also claims there is a viable roadmap for using HBC across many Qualcomm AI accelerators, with HBC Gen 1 set to ship with the AI250 AI accelerator in the first half of 2027.