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Intel Zooms in on "Lakefield" Foveros Package

The fingernail-size Intel chip with Foveros technology is a first-of-its kind. With Foveros, processors are built in a totally new way: not with the various IPs spread out flat in two dimensions, but with them stacked in three dimensions. Think of a chip designed as a layer cake (a 1-millimeter-thick layer cake) versus a chip with a more-traditional pancake-like design. Intel's Foveros advanced packaging technology allows Intel to "mix and match" technology IP blocks with various memory and I/O elements - all in a small physical package for significantly reduced board size. The first product designed this way is "Lakefield," the Intel Core processor with Intel hybrid technology.

Industry analyst firm The Linley Group recently named Intel's Foveros 3D-stacking technology as "Best Technology" in its 2019 Analysts' Choice Awards. "Our awards program not only recognizes excellence in chip design and innovation, but also acknowledges the products that our analysts believe will have an impact on future designs," said Linley Gwennap, of The Linley Group.

Intel Core i5-L16G7 is the first "Lakefield" SKU Appearance, Possible Prelude to New Nomenclature?

Intel Core i5-L16G7 is the first commercial SKU that implements Intel's "Lakefield" heterogenous x86 processor architecture. This 5-core chip features one high-performance "Sunny Cove" CPU core, and four smaller "Tremont" low-power cores, with an intelligent scheduler balancing workloads between the two core types. This is essentially similar to ARM big.LITTLE. The idea being that the device idles most of the time, when lower-powered CPU cores can hold the fort; performance cores kick in only when really needed, until which time they remain power-gated. Thai PC enthusiast TUM_APISAK discovered the first public appearance of the i5-L16G7 in an unreleased Samsung device that has the Userbenchmark device ID string "SAMSUNG_NP_767XCL."

Clock speeds of the processor are listed as "1.40 GHz base, with 1.75 GHz turbo," but it's possible that the two core types have different clock-speed bands, just like the cores on big.LITTLE SoCs. Other key components of "Lakefield" include an iGPU based on the Gen11 graphics architecture, and an LPDDR4X memory controller. "Lakefield" implements Foveros packaging, in which high-density component dies based on newer silicon fabrication nodes are integrated with silicon interposers based on older fabrication processes, which facilitate microscopic high-density wiring between the dies. In case of "Lakefield," the Foveros package features a 10 nm "compute field" die sitting atop a 22 nm "base field" interposer.

Lenovo ThinkPad X1 Fold is a Force Multiplier for Road Warriors at CES 2020

The ThinkPad brand from Lenovo has always represented serious business on the move, right from its IBM origins. At CES 2020, the company unveiled what is possibly the best foldable PC design we've seen till date, the ThinkPad X1 Fold. The X1 Fold is a 13.3-inch tablet that folds perfectly along the middle to either a book-like orientation, or as a laptop, in which the top half becomes the display, and the bottom half your keyboard of whichever possible layout. If a touchscreen keyboard doesn't appeal to you, you can dock an accessory that has a physical keyboard and trackpad.

Under the hood of the X1 Fold is an Intel "Lakefield" Hybrid x86 SoC that combines high-performance and high-efficiency x86 cores and dynamically allots workload to them while power-gating on the fly (a la ARM big.LITTLE). When it comes out mid-2020 (likely a Computex 2020 launch), the ThinkPad X1 Fold will be driven by Windows 10X, a new operating system Microsoft is designing specifically for dual-screen mobile computing devices. The Flex 5G is Lenovo's first business notebook with an integrated 5G modem (in addition to Wi-Fi 6), so you can enjoy high-speed mobile Internet on the move. Lastly, we spotted the Lenovo Ducati notebook, a co-branded product of the company's MotoGP team sponsorship.

Microsoft Unveils First Intel "Lakefield" Device and Surface Lineup with 10th Gen Core

Today, at a launch event in New York City, Microsoft previewed the Surface Neo, a category-defining device co-engineered with Intel. The dual-screen device will be powered by Intel's unique processor, code-named "Lakefield," that features an industry-first architecture combining a hybrid CPU with Intel's Foveros 3D packaging technology. It offers device-makers more flexibility to innovate on design, form factor and experience.

"The innovation we've achieved with Lakefield gives our industry partners the ability to deliver on new experiences, and Microsoft's Neo is trailblazing a new category of devices. Intel is committed to pushing the boundaries of computing by delivering key technology innovations for partners across the ecosystem," said Gregory Bryant, Intel executive vice president and general manager of the Client Computing Group.

Intel Unveils "Lakefield" Heterogenous SoC and "Project Athena"

Intel today unveiled a killer new product with which it hopes to bring about as big a change to mobile computing as Ultrabook did some eight years ago. This effort is a combination of a new mobile computing form-factor codenamed "Project Athena," and an SoC at its heart, codenamed "Lakefield." Put simply, "Lakefield" is a 10 nm SoC that's integrated much in the same way as today's ARM SoCs, which combine IP from various vendors onto a single PoP (package-over-package) Foveros die.

The biggest innovation with "Lakefield" is its hybrid x86 multi-core CPU design, which combines four Atom-class low-power cores, with one Core-class "Sunny Cove" core, in a setup akin to ARM's big.LITTLE. Low-power processing loads are distributed to the smaller cores, while the big core is woken up to deal with heavy loads. The SoC also integrates a Gen 11 iGPU core, partial components to accelerate 802.11ax WLAN, 5G, an PoP DRAM and NVMe storage devices. The reference motherboard based on "Lakefield" is barely larger than an M.2 SSD!

Intel Could Develop its own big.LITTLE x86 Adaptation

big.LITTLE is an innovation by ARM, which seeks to minimize power-draw on mobile devices. It is a sort of heterogeneous multi-core CPU design, in which a few "big" high-performance CPU cores work alongside a few extremely low-power "little" CPU cores. The idea here is that the low-power cores consume much lesser power at max load, than the high-performance cores at their minimum power-state, so the high-performance cores can be power-gated when the system doesn't need them (i.e. most of the time).

Intel finds itself with two distinct x86 implementations at any given time. It has low-power CPU micro-architectures such as "Silvermont," "Goldmont," and "Goldmont Plus," etc., implemented on low-power product lines such as the Pentium Silver series; and it has high-performance micro-architectures, such as "Haswell," "Skylake," and "Coffee Lake." The company wants to take a swing at its own heterogeneous multi-core CPU, according to tech stock analyst Ashraf Eassa, with the Motley Fool.
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