Western Digital Corp. today announced at the RISC-V Summit three new open-source innovations designed to support Western Digital's internal RISC-V development efforts and those of the growing RISC-V ecosystem. In his keynote address, Western Digital's Chief Technology Officer Martin Fink unveiled plans to release a new open source RISC-V core, an open standard initiative for cache coherent memory over a network and an open source RISC-V instruction set simulator.

These innovations are expected to accelerate development of new open, purpose-built compute architectures for Big Data and Fast Data environments. Western Digital has taken an active role in helping to advance the RISC-V ecosystem, including multiple related strategic investments and partnerships, and demonstrated progress toward its stated goal of transitioning one billion of the company's processor cores to the RISC-V architecture.

You may never have heard of SiFive before -and that's perfectly understandable. The startup has just been brought from the ground-up following a round of funding, which netted it some $50.6 million dollars in the old, pre-ICO-preferred ways for funding: venture capital. The objective: to offer other startup companies a way to bring their idealized silicon into actual, custom silicon based on the RISC-V architecture, and then work with them towards achieving actual large-scale production.

The company will have available for customers options of IP and pre-baked designs which they can mix and match according to their needs, alongside small-scale production capability for companies to have their actual product - and test it in real-world conditions - before entering large-scale production. This move by SiFive aims to enable a larger variety of task-specific processor designs, ushering in a new, more liberal area of chip design and production.

Recent articles in the media have raised awareness around the processor security vulnerabilities named Meltdown and Spectre. These vulnerabilities are particularly troubling as they are not due to a bug in a particular processor implementation, but are a consequence of the widespread technique of speculative execution. Many generations of processors with different ISAs and from several different manufacturers are susceptible to the attacks, which exploit the fact that instructions speculatively executed on incorrectly predicted code paths can leave observable changes in micro-architectural state even though the instructions' architectural state changes will be undone once the branch prediction is found incorrect. No announced RISC-V silicon is susceptible, and the popular open-source RISC-V Rocket processor is unaffected as it does not perform memory accesses speculatively.

Western Digital Corp. announced today at the 7th RISC-V Workshop that the company intends to lead the industry transition toward open, purpose-built compute architectures to meet the increasingly diverse application needs of a data-centric world. In his keynote address, Western Digital's Chief Technology Officer Martin Fink expressed the company's commitment to help lead the advancement of data-centric compute environments through the work of the RISC-V Foundation. RISC-V is an open and scalable compute architecture that will enable the diversity of Big Data and Fast Data applications and workloads proliferating in core cloud data centers and in remote and mobile systems at the edge. Western Digital's leadership role in the RISC-V initiative is significant in that it aims to accelerate the advancement of the technology and the surrounding ecosystem by transitioning its own consumption of processors - over one billion cores per year - to RISC-V.