Japanese semiconductor maker Rapidus might miss the planned timeline for its 2 nm node production, as the company is reportedly struggling with its initial attempts at risk production and trial runs. According to a report by the Japan Times, 2 nm volume production at Rapidus facilities will likely be delayed by a few months due to difficulties in 2 nm production, specifically with SRAM. SRAM consists of tiny bitcells that serve as the foundational building blocks for designs operating on one node, and without functional SRAM, it is simply impossible to achieve normal volume production.

There are reportedly other problems, including dust and particle control, which are impacting Rapidus cleanrooms—where the actual silicon is manufactured—to a point where production may be jeopardized altogether. Engineers are working on fixing these problems with the cleanroom and SRAM cells, which should put Rapidus on the right track. Despite these challenges, the company claims that the 2 nm node will arrive on time without any delays, so we are yet to see how these issues will impact their product delivery pipeline.

According to Nikkei, a procurement team from Terafab, the chip venture between Tesla and SpaceX, visited Japan and walked local equipment makers through what it plans to buy. The targets it reportedly shared are gigantic: 1 million wafers per month from 2032 onward, with around 700,000 of those going to memory chips and 300,000 to logic. Nikkei's headline puts that at 40 times the output of Japan's Rapidus. The same split first surfaced in a Jiji Press report last month, which said a single Texas plant would handle both memory and logic, with a pilot fab completed as early as July 2027. Intel is reportedly helping with logic using its 2 nm and 1.4 nm-class technology, while a Taiwanese company has been floated as a technology partner for memory. That could be Nanya, though nothing is confirmed.

For context, Samsung's entire DRAM output was estimated at 650,000 to 700,000 wafers a month late last year, while SK hynix was at about 550,000 earlier this year and hopes to reach roughly 1 million by 2030 or 2031. It isn't clear whether Terafab's memory figure covers DRAM alone or also includes NAND, so the Samsung comparison is a loose one. Musk has also been careful with his own dates. On an October SpaceX call, he put "big error bars" on reaching volume production by Q3 2028, with a first SRAM test chip planned for mid-2027 at Terafab's Austin research lab.

TSMC, the world's largest and most advanced semiconductor manufacturer, has been grappling with stagnant progress in SRAM scaling for years. Since the launch of the N5 5 nm process in 2020, the size of the SRAM 6T bitcell has remained around 0.021 µm². While transistor density in logic elements has increased, memory has not seen similar advancements. However, with the introduction of the A14 node, set for production in 2028, TSMC's 6T SRAM bitcell is expected to shrink significantly to 0.017 µm², marking a 19% reduction. This breakthrough indicates that TSMC has successfully advanced the technology and is ready to bring it to mass production with the A14 node.

TSMC is currently conducting pilot production to assess the viability of this semiconductor node, enabling customers to evaluate how their designs will perform in TSMC's production environment. The progress of the A14 node production is promising, with timelines advancing due to early successes. If pilot production continues smoothly without major yield or production issues, risk production is set to commence in 2027, followed by high-volume manufacturing in 2028. If no significant challenges arise next year, TSMC may even accelerate the production schedule by a few months.

Today, IBM (NYSE: IBM), in collaboration with Siemens, announced new research aimed at advancing IBM's nanostack architecture, a new transistor architecture unveiled by IBM earlier this year. The collaboration will bring together IBM's leadership in semiconductor device innovation and Siemens' expertise in electronic design automation (EDA), process simulation, lithography optimization, and advanced manufacturing software to accelerate the development of nanostack.

Nanostack is the industry's first known three-dimensional, nanosheet-based design, vertically stacking and staggering transistors to pack more transistors onto a chip, with nearly 100 billion transistors in a space the size of a fingernail at its current 7 angstrom node. The design also unlocks the use of different material combinations within each stacked layer to optimize performance and power efficiency of each transistor independent of the other. These innovations power substantial leaps in energy efficiency, performance, and SRAM scaling.

Intel's Foundry chief, Naga Chandrasekaran, spoke with investment bank KeyBanc Capital Markets about Intel Foundry and the future trajectory of its nodes. One of the most intriguing insights is that Intel expects its 14A node to be within 5% of TSMC's A14 node, with both competing in the same sector. What this means exactly is unclear, as there are many factors by which a node is measured. These include transistor switching frequency, power efficiency, and density. The "within 5%" figure could imply a 5% advantage, a 5% disadvantage, or a mix of both, so the technical specifics remain uncertain. Intel's recent nodes, like the shipping 18A, are proving to be efficient and high-performing, but TSMC's nodes are also strong, with both companies continuing development.

Intel plans to start 14A node risk production in the second half of 2027, with high-volume production expected in 2028. The company has processed tens of thousands of 14A wafers in pilot production runs and is now working on yield improvements and minor node adjustments before beginning risk production next year. The 14A node is designed to offer a 15-20% performance improvement at the same power level compared to Intel 18A, or it can be optimized for a 25-35% power reduction at the same performance level. This will be accompanied by up to a 30% improvement in chip density compared to Intel 18A, though it is unclear if this refers to logic or SRAM scaling, as the latter has been challenging for the industry.

Axelera AI has formally launched Europa, its new AI Processing Unit architecture first announced back in October last year. The chip is now available in three form factors: as a chip for custom board designs, a half-height, half-length PCIe card (Edge 232p), and a full-height full-length PCIe card (Server 250p). The Europa AIPU has eight second-generation AI processing cores, 16 RISC-V vector processing cores, 128 MB of L2 SRAM, 200 GB/s DRAM bandwidth, PCIe 4.0 x4 interface and an onboard video decoder. The chip can reach 629 TOPS at a 45 W TDP, with INT4, INT8, and INT16 precision support. The Europa architecture targets inference workloads including agentic systems, vision-language models, generative AI, and computer vision and is the direct successor of Axelera Metis.

The Edge 232p is a single-chip HHHL card with up to 629 TOPS, reaching 83.4 tokens per second on Qwen 30B. It's available in validated configurations inside a Dell XE5 and a Supermicro 111AD. The Server 250p steps up to four Europa AIPUs for over 2,500 TOPS combined, delivering up to 4,205 tokens per second on Qwen3 8B at up to 32.1 tokens per second per watt. In a press release, Axelera says it has a sales pipeline that exceeds $1.5 billion and more than 600 customers across the globe. The company is now working on its first chiplet, the Titania, targeting rack-mount servers and supercomputers.

NEO Semiconductor, a leading innovator in advanced AI and memory technologies, today announced the launch of NEO.AI, its next-generation AI memory platform designed to solve the two most significant memory bottlenecks limiting future artificial intelligence systems: on-chip memory (AI cache) and HBM capacity. As part of the platform launch, the company is officially unveiling X-SRAM, its breakthrough AI on-chip memory technology, alongside the latest progress on 3D X-DRAM, its revolutionary high-capacity HBM technology.

As AI models continue to grow in size and complexity, memory is becoming the primary bottleneck for AI performance. Conventional SRAM scaling has slowed significantly as technology nodes advance, while today's HBM remains constrained by the scaling limitations of conventional 2D DRAM. Together, these limitations form the AI Memory Wall.

During MWC, Fujitsu partnered with networking equipment maker 1FINITY to unveil the first silicon wafers and an engineering sample of its "MONAKA" CPU. Scheduled for release in 2027, the initial Fujitsu MONAKA CPU utilizes the Armv9-A architecture and a 3D chiplet layout that combines a core die with separate SRAM and I/O dies. A single chip features 144 cores, and two-socket configurations can scale up to 288 cores per node. The platform supports 12-channel DDR5, PCIe 6.0 with CXL 3.0, and Arm SVE2 for AI and HPC workloads. Fujitsu has chosen TSMC to manufacture this chip using the 2 nm node, paired with Broadcom's 3.5D eXtreme Dimension System-in-Package (XDSiP) packaging architecture. This packaging allows MONAKA to become a 144-core design featuring four 36-core chiplets. These chiplets are stacked face-to-face with SRAM tiles through hybrid copper bonding, utilizing TSMC's N5 process for the cache layer.

In the pictures below, we can see the silicon complex in its early sample packaging, which shows a large central I/O die, HBM memory around the CPU, and the new packaging technology. Reportedly, this CPU has already reached a working version, with Broadcom shipping the CPU to Fujitsu in late February this year. After initial testing and early performance validation, Fujitsu plans to ship these processors to customers around summer, with mass shipping to commence in 2027. The company envisions this SoC as a powerhouse for AI inference, simulation, and large-scale data processing. It will sell these systems to external customers, who showed great interest in Fujitsu's A64FX when the Fugaku computer came online. Fugaku was the most powerful supercomputer back in 2020, achieving 415.53 PetaFLOPS of FP64 and an impressive HPL-AI score of 1.421 ExaFLOPS using lower FP16 precision. Hence, we expect the new MONAKA CPU to enable much greater speeds and some efficiency improvements as well.

Intel Foundry has published a short video demonstration of its advanced packaging technologies, demoing silicon scaling beyond reticle limits of 830 mm². According to the video, Intel's Foveros 3D and EMIB-T interconnect can scale silicon to 12x reticle size, packaging up to 16 compute dies paired with 24 HBM5 memory modules in a single package. All of this will leverage Intel's 18A—including 18A-P and 18A-PT—and 14A nodes that the company is preparing for mass production and external customers.

The approach involves a sophisticated layering technique where base dies, manufactured using the 18A-PT process, incorporate backside power delivery to enhance logic density and reliability. These base dies house SRAM structures similar to Intel's "Clearwater Forest" architecture. They serve as foundations for compute tiles built on the advanced 14A/14A-E nodes, which feature second-generation RibbonFET transistors and PowerDirect technology. Foveros Direct 3D enables vertical stacking through ultra-fine pitch hybrid bonding, while EMIB-T incorporates through-silicon vias to facilitate higher bandwidth connections between chiplets. This combination achieves scalability beyond reticle limits and will support all HBM standard, including HBM4, HBM5, and future versions.

Marvell recently showcased its custom silicon IP advancements at the Marvell Analyst Day 2025. The company has developed SRAM IP that surpasses industry standards in terms of power efficiency and density. Initially launched in June, their 2 nm SRAM IP now reveals performance figures that highlight its superiority over standard solutions. In a 256K instance comparison, Marvell reports an 80% reduction in total power consumption, a 37% smaller area, and cycle times that are 22% faster. Additionally, Marvell's memory layout is more rectangular, facilitating easier integration into dense SoCs.

Further comparisons with top alternatives show that Marvell's custom SRAM uses 50% less area at the same bandwidth, reduces standby power by 66%, and delivers 17 times more bandwidth per mm² when normalized by area. These improvements are attributed to redesigned clocking and port structures that enhance bandwidth from on-die SRAM. Marvell argues that this architectural approach results in significantly higher bandwidth density and lower power consumption compared to standard dense SRAM IP. In an era where logic scaling continues to outpace memory in modern semiconductor nodes, having custom IP that aggressively boosts SRAM density and reduces power usage is a massive advantage.

GSI Technology, Inc. (Nasdaq: GSIT), the inventor of the Associative Processing Unit (APU), a paradigm shift in artificial intelligence (AI) and high-performance compute (HPC) processing providing true compute-in-memory technology, announced the publication of a paper led by researchers at Cornell University. Findings confirmed that GSI Technology's APU CIM (Compute-In-Memory) architectures can match GPU-level performance for large-scale AI applications with a dramatic reduction in energy consumption due to high-density and high-bandwidth memory associated with the CIM architecture.

Key findings include:

• GPU-class performance - The Gemini-I APU delivered comparable throughput to NVIDIA's A6000 GPU on RAG workloads.
• Massive energy advantage - The APU delivers over 98% lower energy consumption than a GPU over various large corpora datasets, underscoring its efficiency and sustainability.
• Faster and more efficient than CPUs - The APU's unique design allows it to perform retrieval tasks several times faster than standard CPUs, shortening total processing time by up to 80%.

Huawei's newest data center CPU, the KunPeng 930, underwent an analysis and teardown thanks to a creator named Kurnal on YouTube and BiliBili. The package is large, roughly 77.5 mm by 58.0 mm, and combines dense compute tiles manufactured at TSMC's 5 nm node with a sizable I/O die produced at SMIC on a more mature process, a possible 14 nm node. That hybrid split lets Huawei chase SRAM density and core scaling where it matters while shifting I/O and routing to a foundry that can absorb volume and ease supply pressure. Each compute tile contains forty Arm-derived cores tuned as the Taishan family, and the platform can be configured to reach a maximum of 80 cores in dual-die SKUs. The I/O die offers broad connectivity, as evidenced by teardown images that reveal a platform designed for 96 PCIe lanes.

At the component level, the KunPeng 930 shows cache and memory density have been a priority. Inside the compute tiles, there is a pair of private 2 MB L2 caches per core, with approximately 91 MB of shared L3 cache on the same die, representing a significant increase over the previous generation. DDR5 memory controllers are present on these compute tiles, and Huawei's diagrams indicate that there are 12 memory channels per chiplet, resulting in a total of 24 channels per processor. The photographed board shows sixteen DIMM sockets, which implies that not every theoretical memory channel is routed. The processor advertises up to 96 PCIe lanes, although the board only exposes about 80, reflecting routing and cost trade-offs. An SMIC-made I/O die would ease volume production but raise the need for firmware and software tuning to extract peak performance, so we are yet to see how these chips perform in server-centric benchmarks.

Intel has updated its 18A node website with the message, "Intel 18A is now ready for customer projects with the tape outs beginning in the first half of 2025: contact us for more information." The contact hyperlink includes an email where future customers can direct their questions to Intel. Designed as a turnaround node for Intel, 18A carries industry-leading features like SRAM density scaling comparable with TSMC's N2, 15% better performance per watt, and 30% better chip density vs. the Intel 3 process node used in Intel Xeon 6, as well as PowerVia backside-power delivery to increase transistor density.

Other features like RibbonFET are the first to replace FinFET transistors, making gate leakage a tighter control. Interestingly, Intel's first products to use the 18A node are client CPUs "Panther Lake" and "Clearwater Forest" Xeon CPUs for data centers. External Intel Foundry customers using the 18A node include Amazon's AWS, Microsoft for its internal silicon for Azure, and Broadcom exploring 18A-based designs. The process of gaining customers for advanced manufacturing is complex, as many existing Samsung/TSMC customers are not risking their capacity and contracts with established advanced silicon makers. However, if Intel's first few customers prove successful, many others could flock over to Intel's fabs as geopolitical tensions are questioning whether the current models of the semiconductor supply chain are feasible in the future. If US companies and startups decide to move with Intel for their chip manufacturing, Intel could experience a complete recovery.

Intel has unveiled some interesting advances in semiconductor manufacturing at the International Solid-State Circuits Conference (ISSCC), showcasing the capabilities of its highly anticipated Intel 18A process technology. The presentation highlighted significant improvements in SRAM bit cell density. The PowerVia system, coupled with RibbonFET (GAA) transistors, is at the heart of Intel's node. The company demonstrated solid progress with their high-performance SRAM cells, achieving a reduction from 0.03 µm² in Intel 3 to 0.023 µm² in Intel 18A. High-density cells showed similar improvement, shrinking to 0.021 µm². These advancements represent scaling factors of 0.77 and 0.88 respectively, which are significant achievements in SRAM technology, once thought to be done with scaling benefits.

Implementing PowerVia technology is an Intel-first approach to addressing voltage drops and interference in processor logic areas. Using an "around the array" scheme, Intel strategically applies PowerVias to I/O, control, and decoder elements while optimizing bit cell design without a frontal power supply. The macro bit density of 38.1 MBit/mm² achieved by Intel 18A puts the company in a strong competitive position. While TSMC reported matching figures with their N2 process, Intel's comprehensive approach with 18A, combining PowerVia and GAA transistors, could challenge Smausng and TSMC, with long-term aspirations to compete for premium clients currently served by TSMC, including giants like NVIDIA, Apple, and AMD.

Being the leading-edge semiconductor manufacturing company, TSMC actively works on increasing the efficiency of its upcoming nodes, even when they are finalized and ready for high-volume manufacturing. According to a TSMC employee identified as Dr. Kim on X, recent test runs of the 2 nm N2 nodes show a 6% improvement in production yields compared to baseline expectations. This advancement could translate into substantial cost savings for the company's customers when mass production begins in late 2025. However, specific details about whether the gains were achieved in SRAM or logic test chips remain undisclosed. The timing is particularly noteworthy as TSMC prepares to launch its shuttle test wafer services for 2 nm technology in January. The N2 process represents a giant leap for TSMC, marking its first gate-all-around (GAA) nanosheet transistors implementation, the first step to derive from the classical FinFET design.

According to TSMC's projections, chips manufactured using the N2 process will consume 25-30% less power while maintaining the same transistor count and frequency as its N3E node. Additionally, the technology is expected to deliver 10-15% performance improvements and achieve a 15% increase in transistor density. A key innovation in the N2 process is the enhanced design of its GAA nanosheet transistors, which offers improved electrostatic control and reduced gate leakage compared to 3 nm FinFET transistors, given that the gate can be controlled from all sides. This advancement enables smaller high-density transistors to maintain reliable performance through better threshold voltage tuning capabilities. With approximately seven to eight months until full-scale volume production begins, the company has a substantial window to optimize the manufacturing process further and potentially achieve additional yield improvements, although that is less likely.

We are days away from the official November 7 launch of AMD's Ryzen 7 9800X3D CPU with 3D V-Cache, and we are already seeing some estimates of the speedup compared to the last-generation Ryzen 7 7800X3D CPU. According to a Geekbench submission discovered by Everest (Olrak29_) on X, the upcoming AMD Ryzen 7 9800X3D has been spotted running at a clock speed of 5.46 GHz. This is a 260 MHz increase from the official boost frequency of 5.2 GHz, which indicates overclocking has been applied. If readers recall, the last generations of X3D processors had overclocking disabled, and this time, things are looking different thanks to the compute die being placed on top of SRAM. AMD attributes this to CCD being closer to the heat spreader instead of memory and allowing it to spread heat more effectively, ensuring a stable overclock.

Regarding performance, the Ryzen 7 9800X3D outperforms its predecessor, the Ryzen 7 7800X3D, by an impressive 27.4% in the single-core Geekbench v6 test and 26.8% in the multicore test. The last generation CPU scored 2,726 points in single-core and 15,157 points in multicore tests, while the new Zen 5 design has managed to produce 3,473 points in single-core and 19,216 in multicore tests. These results are approximately 27% improvement over the Zen 4, suggesting that the Zen 5 architecture benefits greatly from better SRAM bandwidth and capacity. While these results only come from synthetic benchmarks, they give us a picture of what to expect from this CPU. We have to wait for more real-world test cases to fully conclude the improvement factor.

During the Vision 2024 event, Intel announced its latest Gaudi 3 AI accelerator, promising significant improvements over its predecessor. Intel claims the Gaudi 3 offers up to 70% improvement in training performance, 50% better inference, and 40% better efficiency than Nvidia's H100 processors. The new AI accelerator is presented as a PCIe Gen 5 dual-slot add-in card with a 600 W TDP or an OAM module with 900 W. The PCIe card has the same peak 1,835 TeraFLOPS of FP8 performance as the OAM module despite a 300 W lower TDP. The PCIe version works as a group of four per system, while the OAM HL-325L modules can be run in an eight-accelerator configuration per server. This likely will result in a lower sustained performance, given the lower TDP, but it confirms that the same silicon is used, just finetuned with a lower frequency. Built on TSMC's N5 5 nm node, the AI accelerator features 64 Tensor Cores, delivering double the FP8 and quadruple FP16 performance over the previous generation Gaudi 2.

The Gaudi 3 AI chip comes with 128 GB of HBM2E with 3.7 TB/s of bandwidth and 24 200 Gbps Ethernet NICs, with dual 400 Gbps NICs used for scale-out. All of that is laid out on 10 tiles that make up the Gaudi 3 accelerator, which you can see pictured below. There is 96 MB of SRAM split between two compute tiles, which acts as a low-level cache that bridges data communication between Tensor Cores and HBM memory. Intel also announced support for the new performance-boosting standardized MXFP4 data format and is developing an AI NIC ASIC for Ultra Ethernet Consortium-compliant networking. The Gaudi 3 supports clusters of up to 8192 cards, coming from 1024 nodes comprised of systems with eight accelerators. It is on track for volume production in Q3, offering a cost-effective alternative to NVIDIA accelerators with the additional promise of a more open ecosystem. More information and a deeper dive can be found in the Gaudi 3 Whitepaper.

AI workloads are split into two different categories: training and inference. While training requires large computing and memory capacity, access speeds are not a significant contributor; inference is another story. With inference, the AI model must run extremely fast to serve the end-user with as many tokens (words) as possible, hence giving the user answers to their prompts faster. An AI chip startup, Groq, which was in stealth mode for a long time, has been making major moves in providing ultra-fast inference speeds using its Language Processing Unit (LPU) designed for large language models (LLMs) like GPT, Llama, and Mistral LLMs. The Groq LPU is a single-core unit based on the Tensor-Streaming Processor (TSP) architecture which achieves 750 TOPS at INT8 and 188 TeraFLOPS at FP16, with 320x320 fused dot product matrix multiplication, in addition to 5,120 Vector ALUs.

Having massive concurrency with 80 TB/s of bandwidth, the Groq LPU has 230 MB capacity of local SRAM. All of this is working together to provide Groq with a fantastic performance, making waves over the past few days on the internet. Serving the Mixtral 8x7B model at 480 tokens per second, the Groq LPU is providing one of the leading inference numbers in the industry. In models like Llama 2 70B with 4096 token context length, Groq can serve 300 tokens/s, while in smaller Llama 2 7B with 2048 tokens of context, Groq LPU can output 750 tokens/s. According to the LLMPerf Leaderboard, the Groq LPU is beating the GPU-based cloud providers at inferencing LLMs Llama in configurations of anywhere from 7 to 70 billion parameters. In token throughput (output) and time to first token (latency), Groq is leading the pack, achieving the highest throughput and second lowest latency.

AMD's 3D V-Cache technology utilizes blocks of SRAM stacked on top of the CPU logic die, where CPU cores reside, and allows the processor to access massive pools of cache for applications. However, using this extra level 3 (L3) cache as a RAM disk appears possible, where the L3 SRAM behaves similarly to a storage drive. A big disclaimer here is that this is only possible by exposing the L3 to the CrystalDiskMark benchmark, and no real-world applications can do it in a way that CrystalDiskMark. According to X/Twitter user Nemez (@GPUsAreMagic), the steps to replicate this procedure are: Obtaining an AMD Ryzen CPU with 3D V-Cache, installing OSFMount and creating a FAT32 formatted RAM disk, and running CrystalDiskMark, with values set to values to SEQ 256 KB, Queue Depth 1, Threads 16, and data fill to 0s instead of random.

The results of this experiment? Well, they appear to be rather stunning as the nature of L3 SRAM is that the memory is tiny but very fast and accessible to the CPU, so it can help load data locally before going to the system RAM. With AMD Ryzen 7 5800X3D, the speeds of this RAM disk are over 182 GB/s for reading and over 175 GB/s for writing. In another test, shared by Albert Thomas (@ultrawide219), we managed to see RAM disk based on AMD Ryzen 7800X3D V-Cache, which scores a little less with over 178 GB/s read and over 163 GB/s write speeds. Again, CrystalDiskMark only performed these tests on small allocations varying between 16 MiB and 32 MiB, so no real-world workloads are yet able to utilize this.

Zero ASIC, a semiconductor startup, came out of stealth today to announce early access to its one-of-a-kind ChipMaker platform, demonstrating a number of world firsts:

• 3D chiplet composability enabling billions of new silicon products
• Fully automated no-code chiplet-based chip design
• Zero install interactive RTL-based chip emulation
• Roadmap to 100X reduction in chip development costs

"Custom Application Specific Integrated Circuits (ASICs) offer 10-100X cost and energy advantage over commercial off the shelf (COTS) devices, but the enormous development cost makes ASICs non-viable for most applications," said Andreas Olofsson, CEO and founder of Zero ASIC. "To build the next wave of world changing silicon devices, we need to reduce the barrier to ASICs by orders of magnitude. Our mission at Zero ASIC is to make ordering an ASIC as easy as ordering catalog parts from an electronics distributor."

Ever since the creation of A64FX for the Fugaku supercomputer, Fujitsu has been plotting the development of next-generation CPU design for accelerating AI and general-purpose HPC workloads in the data center. Codenamed Monaka, the CPU is the latest creation for TSMC's 2 nm semiconductor manufacturing node. Based on Armv9-A ISA, the CPU will feature up to 150 cores with Scalable Vector Extensions 2 (SVE2), so it can process a wide variety of vector data sets in parallel. Using a 3D chiplet design, the 150 cores will be split into different dies and placed alongside SRAM and I/O controller. The current width of the SVE2 implementation is unknown.

The CPU is designed to support DDR5 memory and PCIe 6.0 connection for attaching storage and other accelerators. To bring cache coherency among application-specific accelerators, CXL 3.0 is present as well. Interestingly, Monaka is planned to arrive in FY2027, which starts in 2026 on January 1st. The CPU will supposedly use air cooling, meaning the design aims for power efficiency. Additionally, it is essential to note that Monaka is not a processor that will power the post-Fugaku supercomputer. The post-Fugaku supercomputer will use post-Monaka design, likely iterating on the design principles that Monaka uses and refining them for the launch of the post-Fugaku supercomputer scheduled for 2030. Below are the slides from Fujitsu's presentation, in Japenese, which highlight the design goals of the CPU.

TSMC today announced the new 3Dblox 2.0 open standard and major achievements of its Open Innovation Platform (OIP) 3DFabric Alliance at the TSMC 2023 OIP Ecosystem Forum. The 3Dblox 2.0 features early 3D IC design capability that aims to significantly boost design efficiency, while the 3DFabric Alliance continues to drive memory, substrate, testing, manufacturing, and packaging integration. TSMC continues to push the envelope of 3D IC innovation, making its comprehensive 3D silicon stacking and advanced packaging technologies more accessible to every customer.

"As the industry shifted toward embracing 3D IC and system-level innovation, the need for industry-wide collaboration has become even more essential than it was when we launched OIP 15 years ago," said Dr. L.C. Lu, TSMC fellow and vice president of Design and Technology Platform. "As our sustained collaboration with OIP ecosystem partners continues to flourish, we're enabling customers to harness TSMC's leading process and 3DFabric technologies to reach an entirely new level of performance and power efficiency for the next-generation artificial intelligence (AI), high-performance computing (HPC), and mobile applications."

When TSMC introduced its N3 lineup of nodes, the company only talked about the logic scaling of the two new semiconductor manufacturing steps. However, it turns out that there was a reason for it, as WikiChip confirms that the SRAM bit cells of N3 nodes are almost identical to the SRAM bit cells of N5 nodes. At TSMC 2023 Technology Symposium, TSMC presented additional details about its N3 node lineup, including logic and SRAM density. For starters, the N3 node is TSMC's "3 nm" node family that has two products: a Base N3 node (N3B) and an Enhanced N3 node (N3E). The base N3B uses a new (for TSMC) self-aligned contact (SAC) scheme that Intel introduced back in 2011 with a 22 nm node, which improves the node's yield.

Regardless of N3's logic density improvements compared to the "last-generation" N5, the SRAM density is almost identical. Initially, TSMC claimed N3B SRAM density was 1.2x over the N5 process. However, recent information shows that the actual SRAM density is merely a 5% difference. With SRAM taking a large portion of the transistor and area budget of a processor, N3B's soaring manufacturing costs are harder to justify when there is almost no area improvement. For some time, SRAM scaling wasn't following logic scaling; however, the two have now completely decoupled.

Samsung has invested heavily in semiconductor manufacturing technology to provide clients with a viable alternative to TSMC and its portfolio of nodes spanning anything from mobile to high-performance computing (HPC) applications. Today, we have information that Samsung will present its SF4X node to the public in this year's VLSI Symposium. Previously known as a 4HPC node, it is designed as a 4 nm-class node with a specialized use case for HPC processors, in contrast to the standard SF4 (4LPP) node that uses 4 nm transistors designed for low-power standards applicable to mobile/laptop space. According to the VLSI Symposium schedule, Samsung is set to present more info about the paper titled "Highly Reliable/Manufacturable 4nm FinFET Platform Technology (SF4X) for HPC Application with Dual-CPP/HP-HD Standard Cells."

As the brief introduction notes, "In this paper, the most upgraded 4nm (SF4X) ensuring HPC application was successfully demonstrated. Key features are (1) Significant performance +10% boosting with Power -23% reduction via advanced SD stress engineering, Transistor level DTCO (T-DTCO) and [middle-of-line] MOL scheme, (2) New HPC options: Ultra-Low-Vt device (ULVT), high speed SRAM and high Vdd operation guarantee with a newly developed MOL scheme. SF4X enhancement has been proved by a product to bring CPU Vmin reduction -60mV / IDDQ -10% variation reduction together with improved SRAM process margin. Moreover, to secure high Vdd operation, Contact-Gate breakdown voltage is improved by >1V without Performance degradation. This SF4X technology provides a tremendous performance benefits for various applications in a wide operation range." While we have no information on the reference for these claims, we suspect it is likely the regular SF4 node. More performance figures and an in-depth look will be available on Thursday, June 15, at Technology Session 16 at the symposium.

Today at the Intel Vision conference, Habana Labs, an Intel company, announced its second-generation deep learning processors, the Habana Gaudi 2 Training and Habana Greco Inference processors. The processors are purpose-built for AI deep learning applications, implemented in 7nm technology and build upon Habana's high-efficiency architecture to provide customers with higher-performance model training and inferencing for computer vision and natural language applications in the data center. At Intel Vision, Habana Labs revealed Gaudi2's training throughput performance for the ResNet-50 computer vision model and the BERT natural language processing model delivers twice the training throughput over the Nvidia A100-80GB GPU.

"The launch of Habana's new deep learning processors is a prime example of Intel executing on its AI strategy to give customers a wide array of solution choices - from cloud to edge - addressing the growing number and complex nature of AI workloads. Gaudi2 can help Intel customers train increasingly large and complex deep learning workloads with speed and efficiency, and we're anticipating the inference efficiencies that Greco will bring."—Sandra Rivera, Intel executive vice president and general manager of the Datacenter and AI Group