Wednesday, December 24th 2025
Intel Envisions 16 Compute Dies and 24 HBM5 Modules in a Single Package
Intel Foundry has published a short video demonstration of its advanced packaging technologies, demoing silicon scaling beyond reticle limits of 830 mm². According to the video, Intel's Foveros 3D and EMIB-T interconnect can scale silicon to 12x reticle size, packaging up to 16 compute dies paired with 24 HBM5 memory modules in a single package. All of this will leverage Intel's 18A—including 18A-P and 18A-PT—and 14A nodes that the company is preparing for mass production and external customers.
The approach involves a sophisticated layering technique where base dies, manufactured using the 18A-PT process, incorporate backside power delivery to enhance logic density and reliability. These base dies house SRAM structures similar to Intel's "Clearwater Forest" architecture. They serve as foundations for compute tiles built on the advanced 14A/14A-E nodes, which feature second-generation RibbonFET transistors and PowerDirect technology. Foveros Direct 3D enables vertical stacking through ultra-fine pitch hybrid bonding, while EMIB-T incorporates through-silicon vias to facilitate higher bandwidth connections between chiplets. This combination achieves scalability beyond reticle limits and will support all HBM standard, including HBM4, HBM5, and future versions.
As Intel's advanced packaging technology continues to evolve, the company envisions a 5,000 W GPU design utilizing integrated voltage regulators (IVRs). While this might seem extreme, Intel plans to employ the Foveros-B variant to deliver 5 kW GPUs by 2027. Intel has already developed advanced packages for products like the now-discontinued "Ponte Vecchio," and we expect to see similar designs for the upcoming "Jaguar Shores" AI accelerators. With Intel expanding its packaging capacity, it appears that external customers are recognizing it as a true competitor to TSMC's CoWoS designs.
Source:
Intel Foundry
The approach involves a sophisticated layering technique where base dies, manufactured using the 18A-PT process, incorporate backside power delivery to enhance logic density and reliability. These base dies house SRAM structures similar to Intel's "Clearwater Forest" architecture. They serve as foundations for compute tiles built on the advanced 14A/14A-E nodes, which feature second-generation RibbonFET transistors and PowerDirect technology. Foveros Direct 3D enables vertical stacking through ultra-fine pitch hybrid bonding, while EMIB-T incorporates through-silicon vias to facilitate higher bandwidth connections between chiplets. This combination achieves scalability beyond reticle limits and will support all HBM standard, including HBM4, HBM5, and future versions.
17 Comments on Intel Envisions 16 Compute Dies and 24 HBM5 Modules in a Single Package
AMD delivers.
The amount of power/temperature and physical shifting of parts on something that scale is going to be monumental and the possibility of site specific hot spots is going to be hilarious
Gone are the days when designing and fabricating your own chips gave you a competitive advantage. Hence why Intel is the only company left doing so.
Not mentioned is Intel-designed silicon. This is Intel Foundry saying what could be made if AMD or Nvidia or Intel wanted to make something at Intel. Intel packaging services are already in high demand, but it looks like this is partly trying to attract fab customers as well.
Meanwhile, Intel's 18A really has to deliver, if it intends to attract customers other than itself.
1. They may be worried that their design could be adopted by Intel.
2. They may choose not to engage with Intel especially peak seasons because IFS could prioritize with their own products.
3. IFS litho could be optimized for Intel products.For high-NA EUV, that should be around 530 mm^2.
Edit:Like Squared pointed out, Intel Foundry already delivers similar products.
It became an internal only part, cause no one would pay for it... and its successor falcon shores was canceled.
They punted and are hoping to make Jaguar shores competitive but ill not hold my breath.
Of course Arrow Lake ended up being mostly fabbed by TSMC and Ponte Vecchio was underperforming, but that wasn't really the point I was trying to make