Thursday, September 21st 2017

Intel Delays 10nm "Cannon Lake" to Late-2018

Intel is reportedly delaying the roll-out of its first processors built on its 10 nanometer silicon fabrication process, codenamed "Cannon Lake" for the third time since its inception. The first products based on the silicon will now come out only by late-2018. In the meantime, Intel could continue to ride on its new 8th generation Core "Coffee Lake" processors, including the augmentation of an 8-core mainstream desktop (MSDT) part in the second-half of 2018.

Notebook manufacturers are less than enthusiastic about "Cannon Lake," and plan to skip it altogether for its successor, codenamed "Ice Lake," which could come out in 2019. It won't be the first time OEMs have done this, as Intel's 5th generation Core "Broadwell" architecture was mostly skipped over in the notebook and MSDT segments.
Sources: Electronics Weekly, DigiTimes
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15 Comments on Intel Delays 10nm "Cannon Lake" to Late-2018

#1
Blueberries
This is it-- the final frontier. 10nm fabrication is the end of the road for this type of processor scaling and likely the last IPC increase we'll see in CPU production for a long time to come.

(I know there has been success with 7nm neowafers but I don't see a future for it in msdt)
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#2
Prima.Vera
"Blueberries said:
This is it-- the final frontier. 10nm fabrication is the end of the road for this type of processor scaling and likely the last IPC increase we'll see in CPU production for a long time to come.

(I know there has been success with 7nm neowafers but I don't see a future for it in msdt)
Nah, Samsung already has 6nm prototypes running with no issue, while intel already demo some 5nm CPUs.
Even 1nm is on the roadmap after 2020, while going bellow, a different material than Silicon is going to be used... Relax, 10 more years from now on we will still see a 3% performance increase from Intel every year, no worries. :laugh::laugh::laugh:
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#3
Upgrayedd
Fairly confident in a delid and OC of my 4790K to hold out for Tiger Lake. 2019-2020.
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#4
StrayKAT
"Blueberries said:
This is it-- the final frontier.
Does that mean the "Lake" moniker will drop too?
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#5
kn00tcn
"StrayKAT said:
Does that mean the "Lake" moniker will drop too?
the current paradigm of manufacturing will drown into the lakes
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#6
papermaster101
"Prima.Vera said:
Nah, Samsung already has 6nm prototypes running with no issue, while intel already demo some 5nm CPUs.
Even 1nm is on the roadmap after 2020, while going bellow, a different material than Silicon is going to be used... Relax, 10 more years from now on we will still see a 3% performance increase from Intel every year, no worries. :laugh::laugh::laugh:
The later nodes on the roadmap are not shrinks, they are die stacks or improved nodes with the commercial name of a smaller process. Even Samsung's 1 - 2 nm should be what Intel and the ITRS would call at best 6 / 7 nm on the early 2000s. TSMC's 2.5 / 3.5 nm certainly is, going by their slides.
The problem isn't silicon per se, the problem is physics and economic cost. All these silicon alternatives you have seen being flashed around for decades are being used already by the industry on their own niches, so it's not like there is an unaccounted or untested unobtanium of computer chips out there.
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#7
remunramu
2018? No problem, but it better be 25%+ boost from previous generation.
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#8
lyndonguitar
I play games
"StrayKAT said:
Does that mean the "Lake" moniker will drop too?
more likely they will start a new series. This will be the end of core i series. I hope they name the new brand Intel V series.(as a homage to 'Pentium V') Intel V5, Intel V7.

I wonder what's next in store.
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#9
efikkan
"Blueberries said:
This is it-- the final frontier. 10nm fabrication is the end of the road for this type of processor scaling and likely the last IPC increase we'll see in CPU production for a long time to come.
Node shrinks have never yielded any IPC increase…
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#10
GorbazTheDragon
"Blueberries said:
This is it-- the final frontier. 10nm fabrication is the end of the road for this type of processor scaling and likely the last IPC increase we'll see in CPU production for a long time to come.

(I know there has been success with 7nm neowafers but I don't see a future for it in msdt)
Expect the road beyond 10 to be really really slow in terms of die shrinking, but don't expect IPC to bottom out. There have always been incremental improvements in architecture efficiency, we can do more with a 10M transistors now than we could 10 years ago.

"efikkan said:
Node shrinks have never yielded any IPC increase…
IPC increase for equal die size. Max die size has always been in the same ballpark.
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#11
efikkan
"GorbazTheDragon said:

IPC increase for equal die size. Max die size has always been in the same ballpark.
IPC is only a result of the architecture. Since Sandy Bridge we've gone from 32nm -> 22 nm -> 14 nm, while the IPC have barely increased, up to ~15% total in real performance. A lot of die space have been used for other features which are either not performance related or specialized acceleration.
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#12
GorbazTheDragon
"efikkan said:
IPC is only a result of the architecture. Since Sandy Bridge we've gone from 32nm -> 22 nm -> 14 nm, while the IPC have barely increased, up to ~15% total in real performance. A lot of die space have been used for other features which are either not performance related or specialized acceleration.
Each core contains more FPUs, ALUs, etc since before. This is a big part of IPC increases and it's enabled by smaller feature size allowing more powerful cores of the same die area. Take an extreme example like intel 486 vs a modern chip, the amount of power in a single core is way larger and is for the most part enabled by higher transistor density.

Also influences how much latency you incur for a given core size as the larger the area the higher the internal latency, potential minor performance increase.
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#13
efikkan
"GorbazTheDragon said:
Each core contains more FPUs, ALUs, etc since before. This is a big part of IPC increases and it's enabled by smaller feature size allowing more powerful cores of the same die area.
More resources will of course affect IPC, but this has nothing to do with node shrinks, this is architecture. Node shrinks gives more freedom to implement more, but it doesn't improve IPC of a design.

"GorbazTheDragon said:

Also influences how much latency you incur for a given core size as the larger the area the higher the internal latency, potential minor performance increase.
Sure, but very minor.
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#14
GorbazTheDragon
"efikkan said:
More resources will of course affect IPC, but this has nothing to do with node shrinks, this is architecture. Node shrinks gives more freedom to implement more, but it doesn't improve IPC of a design.
Point is architectures with more powerful cores, which are where you see the biggest (but definitely not all) IPC jumps, is enabled exclusively by the steady increase in transistor densities.

Whether these are passed down into a product stack is a completely different matter... remember that while there were 8 generations of quad core MSDT processors from intel, the server CPUs went from 4 to 22 in the first 5
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