Friday, April 24th 2020

DigiTimes: TSMC Kicking Off Development of 2nm Process Node

A report via DigiTimes places TSMC as having announced to its investors that exploratory studies and R&D for the development of the 2 nm process node have commenced. As today's leading semiconductor fabrication company, TSMC doesn't seem to be one resting on its laurels. Their 7 nm process and derivatives have already achieved a 30% weight on the company's semiconductor orders, and their 5 nm node (which will include EUV litography) is set to hit HVM (High Volume Manufacturing) in Q2 of this year. Apart from that, not much more is known on 2 nm.

After 5 nm, which is expected to boats of an 84-87% transistor density gain over the current 7nm node, the plans are to go 3nm, with TSMC expecting that node to hit mass production come 2022. Interestingly, TSMC is planning to still use FinFET technology for its 3 nm manufacturing node, though in a new GAAFET (gate-all-around field-effect transistor) technology. TSMC's plans to deploy FinFET in under 5nm manufacturing is something that many industry analysts and specialist thought extremely difficult to achieve, with expectations for these sub-5nm nodes to require more exotic materials and transistor designs than TSMC's apparent plans
Sources: DigiTimes, via Tom's Hardware
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17 Comments on DigiTimes: TSMC Kicking Off Development of 2nm Process Node

#1
mtcn77
Can we make jokes to this serious announcement?
TSMC is planning to still use FinFET technology for its 3 nm manufacturing node, though in a new GAAFET (gate-all-around field-effect transistor) technology
I seriously wonder what they be achieving with contemporaneous technologies.
Posted on Reply
#2
Dante Uchiha
Intel: We are almost enabling mass production in our 10nm process after almost 5 years. :)
Samsung: We'll have 5nm chips ready by the end of the year, and 3nm is already in the plans.
TSMC: We have already developed the process of 6nm, 5nm, 5nm+, 3nm and 2nm. All will be available in bulk in up to 2 years.
Intel left the group.
Posted on Reply
#3
siki
Dante Uchiha
Intel: We are almost enabling mass production in our 10nm process after almost 5 years. :)
Samsung: We'll have 5nm chips ready by the end of the year, and 3nm is already in the plans.
TSMC: We have already developed the process of 6nm, 5nm, 5nm+, 3nm and 2nm. All will be available in bulk in up to 2 years.
Intel left the group.
I click on comments hoping to read this.
Posted on Reply
#4
dj-electric
Dante Uchiha
Intel: We are almost enabling mass production in our 10nm process after almost 5 years. :)
Samsung: We'll have 5nm chips ready by the end of the year, and 3nm is already in the plans.
TSMC: We have already developed the process of 6nm, 5nm, 5nm+, 3nm and 2nm. All will be available in bulk in up to 2 years.
Intel left the group.
Revisit this post in 21 days.
Posted on Reply
#5
BArms
Which part(s) of the transistors will be 2nm?
Posted on Reply
#6
ARF
dj-electric
Revisit this post in 21 days.
May 16th? What should happen then?
BArms
Which part(s) of the transistors will be 2nm?
Nothing because:
1. It's just marketing for N2.
2. At such dimensions, I think they will find it pretty tricky to control the electrons.
Posted on Reply
#7
Ravenas
TSMC can thank Apple for driving their success.
Posted on Reply
#8
Fluffmeister
I always knew Taiwan was better, no drinking of disinfectant required.
Posted on Reply
#9
theoneandonlymrk
Ravenas
TSMC can thank Apple for driving their success.
Are you serious, I think they have themselves to thank and apple have them to thank too.
Posted on Reply
#10
seronx
ARF
Nothing because:
1. It's just marketing for N2.
2. At such dimensions, I think they will find it pretty tricky to control the electrons.
Basically this, in general the current trend is the actual -nm is generally behind.

TSMC 16nm => ~20-nm Leff (20nm node)
TSMC N7 => ~14-nm Leff (14nm node)
GloFo 14nm => ~20-nm Leff (20nm node)
GloFo 7LP => ~16-nm Leff (16nm node)

5nm should be >10-nm Leff (>10nm node)
3nm should be >7-nm Leff (>7nm node)
2nm should be >5-nm Leff (>5nm node)
Posted on Reply
#11
Dave65
While this is going on, Intel adds another + to their 14 nm lineup.
Posted on Reply
#12
mtcn77
Fluffmeister
I always knew Taiwan was better, no drinking of disinfectant required.
Disinfectants might be it, though. Believe me that guy is a genious tethered to disenchanted fools.
We are only just beginning to understand why this is so. The coronavirus attacks lung cells that make surfactant. This substance helps the air sacs in the lungs stay open between breaths and is critical to normal lung function. As the inflammation from Covid pneumonia starts, it causes the air sacs to collapse, and oxygen levels fall.
Are we going to discuss what administers surfactants into the body? I hope not, don't let the door hit you on the way out...
Posted on Reply
#13
lynx29
Dante Uchiha
Intel: We are almost enabling mass production in our 10nm process after almost 5 years. :)
Samsung: We'll have 5nm chips ready by the end of the year, and 3nm is already in the plans.
TSMC: We have already developed the process of 6nm, 5nm, 5nm+, 3nm and 2nm. All will be available in bulk in up to 2 years.
Intel left the group.
intel stock is still doing really well for itself though. Most people buy blindly or cheap marketing. We are a very niche group of gamers.
Posted on Reply
#14
dj-electric
ARF
May 16th? What should happen then?
That's a great question i can absolutely not give you answers about at this moment. But i really like dropping those hints along threads on TPU. Not many people come and revisit my statements often, which at times i think could be good for me to still be able to make them.
Posted on Reply
#15
MxPhenom 216
ASIC Engineer
mtcn77
Can we make jokes to this serious announcement?


I seriously wonder what they be achieving with contemporaneous technologies.
GAAFET is an improvement to FINFET. FINFET starts to exhibit the same issues that traditional planar FET did back when the industry was trying to get below 22nm but now at sub 10nm sizes. Planar couldn't do it so in comes FINFET with much better leakage and control over the behavior of the channel. GAAFET follows FINFET but now the gate surrounds the channel on all sides for even better control of the FETs switching characteristic and reduction of electrons flowing from the source to drain even with the FET off. As transistors get smaller, controlling the channel gets much more difficult. Close to impossible without totally changing the structure of the FET.



Research of transistor structures indicate that standard FINFET will likely end at 3nm unless TSMC is able to work some magic as indicated in this article. Carbon nanotubes, nanosheets, gate all around FETs could be the next big thing in the world of semiconductors. When I was writing a research paper on this stuff in my semiconductor materials class I predicted GAAFETs would be the next iteration for transistors simply because it only marginally increases the manufacturing complexity of transistor, where as carbon nanotubes/sheets make for much more complex process and a lot more expensive. Hell even from Planar to FINFET the complexity of fabrication went way up since there are a lot more places now for problems to arise. Dimensions of the channel and gate have very little room for variation or the transistor will not function at all.
Posted on Reply
#16
bonehead123
MxPhenom 216
GAAFET is an improvement to FINFET. FINFET starts to exhibit the same issues that traditional planar FET did back when the industry was trying to get below 22nm but now at sub 10nm sizes. Planar couldn't do it so in comes FINFET with much better leakage and control over the behavior of the channel. GAAFET follows FINFET but now the gate surrounds the channel on all sides for even better control of the FETs switching characteristic and reduction of electrons flowing from the source to drain even with the FET off. As transistors get smaller, controlling the channel gets much more difficult. Close to impossible without totally changing the structure of the FET.

Research of transistor structures indicate that standard FINFET will likely end at 3nm unless TSMC is able to work some magic as indicated in this article. Carbon nanotubes, nanosheets, gate all around FETs could be the next big thing in the world of semiconductors. When I was writing a research paper on this stuff in my semiconductor materials class I predicted GAAFETs would be the next iteration for transistors simply because it only marginally increases the manufacturing complexity of transistor, where as carbon nanotubes/sheets make for much more complex process and a lot more expensive. Hell even from Planar to FINFET the complexity of fabrication went way up since there are a lot more places now for problems to arise. Dimensions of the channel and gate have very little room for variation or the transistor will not function at all.
Well thanks, you just saved me about 10000 electrons by using all the words from my next upcoming post....hahahaha ..:roll:..:eek:..:laugh:
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