Monday, August 23rd 2021

AMD Envisions Direct Circuit Slicing for Future 3D Stacked Dies

AMD in its HotChips 33 presentation shed light on the the company's efforts to stay on the cutting edge of 3D silicon packaging technology, especially as rival Intel takes giant strides with 2.5D and 3D packaging on its latest "Ponte Vecchio" and "Sapphire Rapids" packages. The company revealed that it co-developed a pioneering new die-on-die stacking technique with TSMC for its upcoming "Zen 3" CCDs with 3D Vertical Caches, which are 64 MB SRAM dies stacked on top of "Zen 3" CCDs to serve as an extension of the 32 MB on-die L3 cache. The micro-bumps connecting the 3D Vertical Cache die with the CCD are 9-micron in pitch, compared to 10-micron on the production variant of Intel Foveros.

AMD believes that no single packaging technology works for all products, and depend entirely on what it is you're trying to stack. The company spoke on the future of die-on-die stacking. For over a decade, package-on-package stacking has been possible (as in the case of smartphones. Currently, it's possible to put memory-on-logic within a single package, between the logic die and an SRAM die for additional cache memory; a logic die an DRAM for RAM integrated with package; or even logic with NAND flash for extreme-density server devices.
The future could see IP-on-IP dual-logic stacking. Examples of this include cores-on-uncore, or even core-on-core. Imagine stacking the CCDs directly on top of the cIOD or sIOD dies to minimize the PCB footprint of the package; or the holy grail of 3D: stacking cores on top of cores.

A level beyond this would be splitting up the core itself into bits, and stacking them up. This could see the hottest components, such as the execution stage with its FP and INT pipelines on a different die than the relatively cooler front-end and load-store units; while the relatively coolest L1 and L2 caches, sit on the lowest slices.
The distant future of silicon stacking sees individual circuits spread across multiple stacked dies, with TSVs (through-silicon vias) connecting them. With each generation shift, AMD expects TSV sizes (and densities) to increase.
Source: ComputerBase.de
Add your own comment

14 Comments on AMD Envisions Direct Circuit Slicing for Future 3D Stacked Dies

#1
ARF
Pff... :banghead:

Posted on Reply
#3
badboy87
More cores but also even more ways to improve efficiency with IMC, cache or iGPU, servers CPU's will benefit the most. Cache latency could finally get close to 0(in theory) if TSV's get improved each gen & whatever other tech they come up with. Maybe that leak from 2018(if I remember correctly) where a server CPU had multiple stacked dies with 8gb or more of HBM2 acting as cache. The future is interesting to say the least & it will all trail to GPU's as well. Immagine 8gigs or more of HBM2 cache on a future GPU, being stacked it will leave room for more chips like in ARM designs(& Apple of course) to handle ray tracing or even more complex, path tracing.
Posted on Reply
#4
Mysteoa
I'm actually becoming more interested in those stacking technologies than the end product performance.
Posted on Reply
#5
DeathtoGnomes
What no 'glue' comments?

If this meant a shrink in die sizes, it would only be temporary. Could this mean more cores packed into current dies sizes tho?
Posted on Reply
#6
TheLostSwede
DeathtoGnomesWhat no 'glue' comments?

If this meant a shrink in die sizes, it would only be temporary. Could this mean more cores packed into current dies sizes tho?
It's staples, not glue...
Posted on Reply
#7
JAB Creations
z1n0xFeel free to show those noobs at AMD how to design processors.
jobs.amd.com/search/
Fanboys are butthurt because they really want to see AMD destroyed so they can blow $600 on bottom of the barrel Celerons because all they have left are their overbloated egos.
Posted on Reply
#8
Punkenjoy
ARFPff... :banghead:

well it work

but today, we can say it's make more cash.. errr Cache ! :D

The more core approach wouldn't work if they didn't had performance on top of that.
Posted on Reply
#9
ZoneDymo
ARFPff... :banghead:
dont really get that, Intel is doing the same thing in an effort to keep up...8700k 2 more cores, 9900k 2 more cores, 10900k 2 more cores 11900k....oh dear what the hell did we create??!!!? 2 less cores, 12900k freaking 8 more cores, eco cores but still.
Posted on Reply
#10
ThrashZone
ZoneDymodont really get that, Intel is doing the same thing in an effort to keep up...8700k 2 more cores, 9900k 2 more cores, 10900k 2 more cores 11900k....oh dear what the hell did we create??!!!? 2 less cores, 12900k freaking 8 more cores, eco cores but still.
Hi,
11900k two less cores yes but more cache single core improved a lot

Then added 8 more small cores which I'm guessing they used to just disable them due to binning they were so power hungry now used at lower frequency.
Pretty interesting 16 core 16 thread a 10960x equivalent "16 less threads though" if there was one that can boost to 5.3 out the box :/
Posted on Reply
#11
Richards
This will interesting on gpu's imagine stacking 5 rx 6900xt 100 teraflops in your hand... intel's ponte vecchio is getting close
Posted on Reply
#14
eidairaman1
The Exiled Airman
Dear AMD, make HBM 3.0 a certain cache level and GDDR6X the main ram.
Posted on Reply
Add your own comment