Monday, September 11th 2023
Die-shot Suggests "Phoenix 2" is AMD's First Hybrid Processor
The 4 nm "Phoenix 2" monolithic APU silicon powering the lower end of AMD's Ryzen 7040-series mobile processors, could very well be the company's first hybrid core processor, even though the company doesn't advertise it as such. We first caught whiff of "Phoenix 2" back in July, when it was described as being a physically smaller chip than the regular "Phoenix." It was known to have just 6 CPU cores, and a smaller iGPU with 4 RDNA3 compute units; in comparison to the 8 CPU cores and 12 compute units of the "Phoenix" silicon. At the time a lack of 2 CPU cores and 8 CUs were known to be behind the significant reduction in die size from 178 mm² to 137 mm², but it turns out that there's a lot more to "Phoenix 2."
A die shot of "Phoenix 2" emerged on Chinese social media platform QQ, which reveals two distinct kinds of CPU cores. There are six cores in all, but two of them appear larger than the other four. The obvious inference here, is that the larger cores are "Zen 4," and the smaller ones are the compacted "Zen 4c." The "Zen 4c" core has the same core machinery as "Zen 4," albeit it is re-arranged to favor lower area on the die. The trade-off here is that the "Zen 4c" core operates at lower voltages and lower clock-speeds than the regular "Zen 4" cores. At the same clock speeds, both kinds of cores have an identical IPC. The two also have an identical ISA, so any software threads migrating between the cores will not encounter runtime errors. Unlike Intel Thread Director, AMD can use a less sophisticated software-based solution to ensure that the right kind of workload is allocated to the right kind of cores, and prevent undesirable migration between the two kinds of cores. Unlike the hardware-based Thread Director, AMD's solution can be continually updated.
Sources:
HXL (Twitter), VideoCardz
A die shot of "Phoenix 2" emerged on Chinese social media platform QQ, which reveals two distinct kinds of CPU cores. There are six cores in all, but two of them appear larger than the other four. The obvious inference here, is that the larger cores are "Zen 4," and the smaller ones are the compacted "Zen 4c." The "Zen 4c" core has the same core machinery as "Zen 4," albeit it is re-arranged to favor lower area on the die. The trade-off here is that the "Zen 4c" core operates at lower voltages and lower clock-speeds than the regular "Zen 4" cores. At the same clock speeds, both kinds of cores have an identical IPC. The two also have an identical ISA, so any software threads migrating between the cores will not encounter runtime errors. Unlike Intel Thread Director, AMD can use a less sophisticated software-based solution to ensure that the right kind of workload is allocated to the right kind of cores, and prevent undesirable migration between the two kinds of cores. Unlike the hardware-based Thread Director, AMD's solution can be continually updated.
62 Comments on Die-shot Suggests "Phoenix 2" is AMD's First Hybrid Processor
You talked about a P-core that is 'half-used', in which you seem to be talking about one thread running in one of the two hardware threads. Will scheduling a new task on the other hardware thread end up harming the performance of the first? Maybe.
There is actually no way of knowing without analyzing exactly what each of those threads are doing. For all we know, the first thread might be stalled because it's accessing some peripheral(say a SSD) that has a latency in the orders of microseconds(note clocks are in nanoseconds or less range for GHz), if it's already not using the core resources then it likely won't matter. Same thing for say, the first thread doesn't use FP/Vector code and the second one does use it very heavily. Or etc etc, threads can end up stalling for whatever reason(and OoO execution tries to hide that but it's not perfect) and so one thread basically has all core resources for some time.
Also, it's not as simple as your solution seems to suggest, you are just locking threads on core types as they are spawned. A good reason to start with is that any modern OS will have more than a hundred threads running at the same time...
Well, there is a lot of reasons, but this is already too long.
So in a 15W laptop processor, it's quite possible and I think more likely than not that two Zen 4 plus four Zen 4c will be faster in most tasks than six Zen 4 cores.
The only thing that matters is the performance & with a shared L3 it looks like there could be minimal difference there!
There is very likely a reason why they have chosen to only use the 6T pseudo-dual port memory cell for Zen 4c and not the normal cores. Those details are likely going to bring clocks considerably down.
About shared L3, it can also depend if they are doing a single CCX or not. I remember that there were stuff about a 4 cores Zen 5 and 8 cores Zen 5c APU(or was it Zen 4 variants for both?) that had each of the core types in one CCX. The new memory cells might also be of higher latency too, it doesn't contradict with anything AMD said about Zen 4c afaik since that isn't viewed as part of the architecture and they only said the architecture remains the same.
Either way, the result is likely that it isn't going to clock anywhere as high as normal Zen 4 and it's also going to have different V/F curves.
What you're saying is also not unheard of, in fact *dozer probably had some of these higher density variants on 28nm(?) IIRC which were supposedly designed to save space. It was around that timeline, though I'm not 100% sure if it were the same products.
What's different is their microarchitecture, which is the inner workings of the CPU core. Zen 4 and Zen 4c on the other hand have nearly identical microarchitectures. They're differentiated by tracing, layout, and cache, with AMD claiming that the end result is identical performance when at the same clock speed. But a Golden Cove core is a lot faster than a Gracemont core when running at the same clock speed.
If you are talking about performance, then yes, for sure, there is a huge difference.
Are you talking about specific MSRs? That does seem to have a difference, specially for the performance counters but that isn't meaningful in the discussion. The difference we are talking about is what it can execute or not at different performance levels, sure a Golden Cove is going to be much faster than a Gracemont, but so is going to be Zen 4 vs Zen 4c, which is where the complication of scheduling arrives.
perfmon-events.intel.com/ahybrid.html
Noting that people have been implementing the same core but in different ways for quite some time. There are plenty of A53 SoCs that have two clusters running at different clocks.
Practically, no.
- Cores get threads allocated in order of their speed with thread 1 going to core 0, thread 2 going to core 1, and so on
- Once the number of threads in the active task reaches the number of cores, then simultaneous mulithreading kicks in and again threads are allocated in order of core speed
As can be seen from the above, for a hypothetical process that can utilize 12 threads, it'll get scheduled onto the Zen 4 cores first (2 threads) and then 4 threads will be scheduled onto the Zen 4c cores. The remaining 6 threads will also be scheduled in a similar fashion. If it spawned only 2 threads, then they will be scheduled onto the Zen 4 cores.In other words, some losses from sub-optimal scheduling are unavoidable if you have faster and slower cores.
BTW, this concept is much older than E-cores on 12th gen Intel. They had Xeon chips with cores with different clock limits way before.