Monday, September 11th 2023
Die-shot Suggests "Phoenix 2" is AMD's First Hybrid Processor
The 4 nm "Phoenix 2" monolithic APU silicon powering the lower end of AMD's Ryzen 7040-series mobile processors, could very well be the company's first hybrid core processor, even though the company doesn't advertise it as such. We first caught whiff of "Phoenix 2" back in July, when it was described as being a physically smaller chip than the regular "Phoenix." It was known to have just 6 CPU cores, and a smaller iGPU with 4 RDNA3 compute units; in comparison to the 8 CPU cores and 12 compute units of the "Phoenix" silicon. At the time a lack of 2 CPU cores and 8 CUs were known to be behind the significant reduction in die size from 178 mm² to 137 mm², but it turns out that there's a lot more to "Phoenix 2."
A die shot of "Phoenix 2" emerged on Chinese social media platform QQ, which reveals two distinct kinds of CPU cores. There are six cores in all, but two of them appear larger than the other four. The obvious inference here, is that the larger cores are "Zen 4," and the smaller ones are the compacted "Zen 4c." The "Zen 4c" core has the same core machinery as "Zen 4," albeit it is re-arranged to favor lower area on the die. The trade-off here is that the "Zen 4c" core operates at lower voltages and lower clock-speeds than the regular "Zen 4" cores. At the same clock speeds, both kinds of cores have an identical IPC. The two also have an identical ISA, so any software threads migrating between the cores will not encounter runtime errors. Unlike Intel Thread Director, AMD can use a less sophisticated software-based solution to ensure that the right kind of workload is allocated to the right kind of cores, and prevent undesirable migration between the two kinds of cores. Unlike the hardware-based Thread Director, AMD's solution can be continually updated.
Sources:
HXL (Twitter), VideoCardz
A die shot of "Phoenix 2" emerged on Chinese social media platform QQ, which reveals two distinct kinds of CPU cores. There are six cores in all, but two of them appear larger than the other four. The obvious inference here, is that the larger cores are "Zen 4," and the smaller ones are the compacted "Zen 4c." The "Zen 4c" core has the same core machinery as "Zen 4," albeit it is re-arranged to favor lower area on the die. The trade-off here is that the "Zen 4c" core operates at lower voltages and lower clock-speeds than the regular "Zen 4" cores. At the same clock speeds, both kinds of cores have an identical IPC. The two also have an identical ISA, so any software threads migrating between the cores will not encounter runtime errors. Unlike Intel Thread Director, AMD can use a less sophisticated software-based solution to ensure that the right kind of workload is allocated to the right kind of cores, and prevent undesirable migration between the two kinds of cores. Unlike the hardware-based Thread Director, AMD's solution can be continually updated.
62 Comments on Die-shot Suggests "Phoenix 2" is AMD's First Hybrid Processor
For Intel's Big/Little design, this can and frequently does result in degraded performance for the thread shifted to an E-Core, because the "little" cores are of a different(less efficient) design and thus much lower IPC. With the AMD version of it in this example, the same dynamic doesn't exist because the "little" core is functionally identical to the "Big" core, just slower clocking, which means the IPC is the same, but the clock speed is slower.
Put another way, Intel's Big/little design results is significant degradation of thread performance due to the differences not only in clock speed but in core instruction execution capabilities. AMD's Big/Little seems a much better way of doing it as the difference is in clock speed alone.
Does this make sense?True, but they were all the same cores IIRC. The per-core clock limitations were microcode imposed.
Thank god it's not happening on intel thanks to the thread director
Yeah, I am sure thread director works perfectly, which is only possible if it can see into the future.
Unless you were being sarcastic, in which case I apologize.
However my research and investigation into improving things has led me to learn some exciting discoveries about CPU scheduling in windows and the hidden power schema settings, I have started documenting it as well, however the few attempts I have tried to share some of this stuff on the net, no one has bitten, I seem to be the only one excited by it. :)
W1zzard briefly got interested but only on the NVME power saving states.
But - still, what do you mean "low bar". What would be the high bar?
Unlike desktops with 142-230W package power, mobile chips really do clock all the way down under all-core loads. The 15W 6800U, for example, really does drop from 4.7GHz on single-threaded loads to under 3GHz when rendering. The 6800U's eight full-fat Zen4 cores are already operating in a way similar to 2x Zen4 and 6x Zen4C, simply because there are "preferred cores" which are the two marked as the best for high boost clocks. By the time the third core is engaged, clocks have already dropped 500MHz, and they'll lose another GHz as the rest of the cores are loaded and the laptop approaches its STAPM limits.
The clocks of Zen4C will definitely be limited by their own stability at sensible voltages, but many of the cores in a full-fat Zen4 processor are already limited anyway by power targets, so the die area spent on giving them the potential ability to clock higher is going to waste, since if there's ever power budget to spare, the cores that that get boosted to 4.7GHz are the two preferred cores.
In practice, this means the Zen4c cores will have different power/frequency curves than Zen4.
It should be a bit like ARMs big vs. LITTLE frequency curves, though less far apart because it's still essentially the same core.