Discord is rewriting its desktop app in Rust and dropping Electron, and the early numbers look very promising. Discord CTO and co-founder Stanislav Vishnevskiy posted a Task Manager screenshot on X showing the new client, listed as "Discord Phoenix," using just 290.2 MB of RAM. In the same screenshot, Steam's WebHelper sits at 856 MB and Battle.net at 344 MB. That's a big drop, as Discord said late last year that its current Windows client normally stays under 1 GB, and it even tested auto-restarting the app once it crossed 4 GB. Vishnevskiy also shared a side-by-side clip on two laptops showing the new client booting much faster, adding that clicking around "feels instant."

Mobile is getting the same treatment. According to Vishnevskiy, Discord is dropping React Native as well, so the mobile apps will keep their native interface while sharing app code with the desktop client through Rust. The new client is built on GPUI, the Rust UI framework from the team behind the Zed code editor, rather than Tauri as many had guessed. There's no release date yet, and Discord only says it hopes to get it into testing with users soon.

Following record second-quarter earnings, TSMC has confirmed one of its most ambitious expansion plans in the United States. Earlier this year, TSMC was reportedly preparing a $100 billion investment package to add four more fabs to its Arizona facility. Now, it seems the decision has been finalized, and TSMC is increasing its investment in the Arizona facilities. Approximately $165 billion has already been invested in Arizona, and the additional $100 billion will make this one of the largest external investments in the U.S. Interestingly, TSMC is not alone in this investment round. Its supply chain partners are expected to contribute about $30 billion of the $100 billion total. This means many more players are gathering funds to establish new supply chain independence.

In January, TSMC reportedly purchased an additional 900 acres of land directly across the highway from the existing site north of Phoenix, preparing to expand its campus. This extra production capacity will be supported by an estimated $100 billion of additional funding that TSMC is willing to invest in the U.S., despite also making simultaneous investments back home in Taiwan.

Intel has reportedly resolved all yield issues it experienced with its 18A node over the past few months. According to the sell-side equity research firm BlueFin Research Partners, Intel has fixed these yield issues, making the high-volume production of its latest node sustainable from both a manufacturing yield and economic standpoint. Readers may recall that late last year, Intel confirmed that 18A yields were improving by about 7% per month over several months. This trend continued into the launch of the first 18A product, codenamed "Panther Lake," up until today, when the yield issues have reportedly been resolved. For a mature node, this usually means defect rates of D0=0.1 or D0=0.2, and it is likely that Intel has now achieved the lower end of that spectrum with the node advancements and months of 18A high-volume production.

Regarding manufacturing capacity, the report notes that Intel's 18A is produced at two sites: Fab 52 in Phoenix, Arizona, and another in Hillsboro, Oregon. These fabs currently produce about 30,000 wafers per month with the 18A printing. This capacity is currently sufficient for Intel's internal production, such as the "Panther Lake" processors, but additional capacity will be needed for other internal products.

TSMC has allocated an additional $20 billion to expand its facility in Phoenix, Arizona, at the Fab 21 site. According to the latest TSMC board resolution meeting, TSMC Arizona, a subsidiary of TSMC, will receive up to $20 billion for now, with the possibility of further capital injections in the future. This resolution supports the expansion of TSMC's Fab 21 site with additional land purchases, expensive EUV equipment, and more semiconductor manufacturing tools. The company has already invested about $65 billion in ongoing Arizona projects and pledged an additional $100 billion in capital expenditure on top of that. The total TSMC Arizona capital expenditure is projected to reach $165 billion, with parts of the additional $100 billion package being gradually unlocked, as seen in today's board meeting resolution.

Interestingly, TSMC Arizona reportedly generated about $514 million in profit last year, its first year of operations. Given TSMC's gross margins of about 66%, this suggests that Fab 21 generated approximately $1.5 billion in revenue. TSMC does not explicitly separate revenue streams from each fab publicly, but these numbers are impressive considering the fab has only been operational for a year. Typically, a fab's first-year performance is not this strong, but it seems TSMC remains an industry leader in this area as well.

Last week, news broke that Lenovo had bought Phoenix Technologies' firmware (BIOS) technology business and now it looks like AMI—also known as American Megatrends Inc—is about to get a new owner, namely Lattice Semiconductor. That leaves Taiwanese Insyde Software as the only independent UEFI/BIOS developer in a market that at least on the desktop side has been largely ruled by AMI and is likely to continue to be so, even with AMI now being a subsidiary to Lattice Semiconductor.

Lattice is offering US$1.65 billion in cash and stock for AMI, which is a privately held company today. For those unfamiliar with Lattice, the company makes a range of FPGA solutions for a wide range of markets and is a competitor with AMD's Xilinx subsidiary and Altera, which is part owned by Intel. It's not entirely clear what the synergy is between Lattice and AMI, but a statement by Lattice CEO Ford Tamer suggests that the company thinks it might help its customers "deploy complex systems faster and with greater confidence" under Lattice's "everywhere companion chip strategy". Time will tell if this will lead to changes to AMI's current customers or not, since as the biggest UEFI/BIOS vendor out there—used by almost all mainstream motherboard makers and many other x86/x64 hardware makers—they have something of a unique position in the market.

Lenovo Group Limited (HKSE: 992) (ADR: LNVGY) (together with its subsidiary, "Lenovo" or the "Group") today announced it has completed the acquisition of Phoenix Technologies' firmware (BIOS) technology business registered in Dublin, Ireland, including its related intellectual property and expertise. The acquisition brings firmware development and additional core software expertise in-house, enhancing Lenovo's ability to manage critical firmware across its entire PC portfolio and, over time, across other AI-enabled devices.

"This transaction is a strategic step forward for Lenovo," said Luca Rossi, President of Intelligent Devices Group, Lenovo. "By bringing firmware development in-house, we are strengthening our core engineering capabilities and gaining greater control over one of the most critical layers of the computing experience. This will enable us to accelerate innovation, enhance security, and deepen our vertical integration, while also unlocking meaningful cost efficiencies. With its strong heritage and leadership in firmware, Phoenix Technologies brings differentiated expertise that will further strengthen our portfolio."

TSMC is reportedly planning to announce the addition of four new fabs at its Phoenix, Arizona site, known as TSMC Arizona. According to the Financial Times, TSMC will add four additional fab buildings at its Arizona campus, worth about $100 billion, with an official confirmation expected as early as April, just two months from the time of writing. In January, TSMC reportedly purchased additional 900-acres of land directly across the highway from the existing site north of Phoenix, preparing to expand its campus across. That extra production capacity will be supported by an estimated $100 billion of additional funding that TSMC is willing to spend on U.S. soil, despite making additional simultaneous investments back home in Taiwan.

However, many of the deal's specifics are still uncertain. According to Commerce Secretary Howard Lutnick, about $100 billion of those pledges are firm, which means that the total value of TSMC's investment in Arizona will amount to $265 billion. About $165 billion has already been invested in Arizona, and another $100 billion will make this one of the highest ever external investments on U.S. soil. Interestingly, TSMC is not alone in this investment round, as its supply chain partners are expected to contribute about $30 billion of the $100 billion figure, meaning that many more players are gathering funds to form the new supply chain independence.

Last autumn, AMD provided an update regarding developmental progress of its openSIL open-source project. According to Raj Kapoor's presentation at last year's OCP Global Summit, the Red Team intends to publish its sixth-generation "Zen 6"-based EPYC "Venice" CPU openSIL sources at some point in 2026. The company's lead firmware architect reiterated that the newer silicon-initialization stack will eventually replace the familiar legacy AGESA firmware line. As of last summer, only one section of AMD's "Zen 5" family has received openSIL support—the EPYC 9005 "Turin" server processor product range. Earlier this week, a 3mbdeb blog entry detailed a compelling experiment that involved the initial "enabling (of) AMD AM5 'Phoenix' support in Coreboot." In the past, this Polish open-source consulting company has experimented with unusual ports of OpenSIL and Coreboot (via the Dasharo distribution). NLnet Foundation funding provided a secure base to start 3mbdeb's Gigabyte MZ33-AR1 porting project, leading to present-day tinkering with MSI's PRO B850-P consumer-grade mainboard design.

Mid-way through their post, they detail a handful of problems, including: "some issues may arise when parsing combo images for AM5 desktop platforms. The desktop images are more complex than server ones. A single PSP (Platform Security Processor) directory may support multiple CPU families, whereas on servers, each CPU family required separate PSP directory. This adds complexity, a need to distinguish PSP directories from each other, and determine the supported CPUs by given directory." So far, the MSI B850-P Pro-based tests have reached a phase of development that is "just enough to (achieve) boot." When outlining a next major milestone, 3mbdeb intends to: "add basic support for desktop AM5 'Phoenix' platform to distinguish mobile CPUs from desktop CPUs in Coreboot. This will serve as a base to cover the differences between the mobile and desktop Phoenix SoCs/APUs." They stress that their 'Phoenix' OpenSIL project is still in a "Proof of Concept" stage, so "not intended for production use." In summary, 3mbdeb's firmware engineer (Michał Żygowski) recommends that external testers wait for the arrival of "exciting" future releases.

Pleasing progress at TSMC's Arizona location has resulted in company leadership expediting a "push into advanced node deployment." Mid-October reports cited an increased domestic demand for 2 nm-class wafer products. Despite the foundry industry leader and NVIDIA's public celebration of debut "made in the USA" NVIDIA "Blackwell" wafers, TSMC's Phoenix-adjacent campus lacks in one key area: advanced packaging. Not long after the conclusion of festivities, computer hardware news outlets highlighted Fab 21-produced (4 nm) Blackwell products being sent overseas—specifically, back to Taiwan—for Chip on Wafer on Substrate (CoWoS) treatments.

Later on in October, TechPowerUp's AleksandarK covered the importance of advanced packaging on North American soil. His special editorial piece focuses on Intel Foundry's potential advantages in this area of expertise; thus poised to take a leading position within the region's semiconductor industry. Yesterday, Taiwan's Liberty Times outlined a major near-future change for one section's of TSMC Arizona's vast spread: "(leadership) plans to convert the land of the planned sixth phase fabrication plant (P6 fab) into an advanced packaging (AP) plant. If the construction goes smoothly, it is expected to be installed as early as the end of 2027 and enter the pre-production stage." Some of the claimed inside track timelines seems to roughly align with previous reports of TSMC and Amkor Technology's $7 billion forthcoming "advanced outsourced semiconductor packaging and testing" facility.

AMD used the Open Compute Project Global Summit in San Jose to provide an update on openSIL, its initiative to replace the legacy AGESA firmware with an open silicon-initialization stack, with timelines for CPUs based on the "Zen 6" IP. Chief Firmware Architect Raj Kapoor presented the latest developments and confirmed that slides and a video of the talk are now available to the public. As part of the update, AMD released the openSIL Firmware Architecture Specification 1.0 and initial platform code for its "Phoenix" client SoCs, marking a shift from proof-of-concept work to wider platform availability. Kapoor also outlined a practical release schedule for future platforms. AMD reiterated that it will initially keep some platform sources under NDA until product launch, then release open-source platform code approximately one quarter after shipping.

According to this schedule, AMD plans to publish the "Venice" 6th Gen EPYC openSIL sources in 2026, suggesting a Venice product launch by Q3 in 2026, and to release the "Medusa" Ryzen CPUs based on "Zen 6" sources in the first half of 2027. The openSIL is designed as a modular, three-part static library written to modern C standards, intended to integrate seamlessly with any x86 host firmware while remaining scalable for different customer needs. Beyond timelines and deliverables, AMD envisioned openSIL as an effort to enhance transparency, speed up integration for hyperscalers, and improve security through auditable code. The project will allow public pull requests, although contributions will be reviewed to protect sensitive microarchitectural IP. This balance between openness and protection was a recurring theme in the presentation, as AMD seeks to open more of its firmware for community collaboration while managing to expose just enough of core design details that drive its CPUs.

AI has ignited a new industrial revolution. NVIDIA and TSMC are working together to build the infrastructure that powers the world's AI factories, right here in America. NVIDIA founder and CEO Jensen Huang today visited TSMC's semiconductor manufacturing facility in Phoenix to celebrate the first NVIDIA Blackwell wafer produced on U.S. soil, representing that Blackwell has reached volume production. Onstage at the celebration, Huang joined Y.L. Wang, vice president of operations at TSMC, to sign the Blackwell wafer, commemorating a milestone that showcases how the engines of the world's AI infrastructure are now being constructed domestically. This bolsters the U.S. supply chain and onshores the AI technology stack that will turn data into intelligence and secure America's leadership for the AI era.

"This is a historic moment for several reasons. It's the very first time in recent American history that the single most important chip is being manufactured here in the United States by the most advanced fab, by TSMC, here in the United States," Huang said at the event. "This is the vision of President Trump of reindustrialization - to bring back manufacturing to America, to create jobs, of course, but also, this is the single most vital manufacturing industry and the most important technology industry in the world."

Researchers from ETH Zurich and Google have shown that SK Hynix DDR5 modules remain vulnerable to a new Rowhammer variant they call Phoenix (CVE-2025-6202), even with on-die ECC memory modules. The attack can be executed in only 109 seconds, making it a very realistic threat. By reverse engineering the built-in DRAM mitigation (TRR) for the already existing Rowhammer exploit, the team found a blind spot in the refresh-sampling logic: the mitigation's sampling period repeats every 128 tREFI intervals and, within those intervals, the first two of four sub-intervals are "lightly sampled." Leveraging this, the researchers crafted two novel long-running hammer patterns: a shorter 128-tREFI pattern and a much longer 2608-tREFI pattern. They later coupled them with a new self-correcting refresh synchronization method that realigns the attack whenever a refresh is missed. This synchronization is what lets Phoenix maintain alignment across thousands of refresh intervals, something prior routines like Zenhammer could not do reliably.

On 15 SK Hynix DDR5 modules, manufactured between late 2021 and late 2024, every module flipped bits under one of the two patterns. The 128-tREFI pattern was about 2.62× more effective on average. The team observed thousands of bit flips per DIMM and turned those flips into real-world primitives: page-table corruption, yielding arbitrary read/write access, extraction of valuable RSA-2048 keys from co-located VMs in many cases, and local privilege escalation by corrupting the sudo binary on some DIMMs. To increase the probability of hitting a vulnerable refresh offset (only 2 of 128 offsets are vulnerable, which is 1.56%), they run four shifted pattern instances across each of the four banks in parallel, boosting the hit probability by 16× to roughly 25%.

AMD's openSIL project, a solution for open CPU silicon initialization code aimed at replacing traditional AGESA, has reached another milestone. Back in February, we reported on AMD promising full support for "Turin" and "Phoenix" server and client SoCs. The company initially targeted the end of 2024 for the release of proof-of-concept code, but failed to meet this deadline. A new target was subsequently set for the first half of 2025. As we roll into the second half, AMD openSIL now supports only the EPYC 9005 series Turin server processors, with Phoenix client SoCs still in development. AMD firmware engineers explained: "Currently, the Phoenix openSIL PoC release is still being worked on internally at AMD. We have encountered some delays in obtaining the necessary approvals to open-source the code, which has impacted our timeline. We are actively working to resolve these issues and are making every effort to expedite the process."

The path towards a fully open-source silicon initialization code is difficult, as it can expose many microarchitectural details. These are usually closely protected, as IP from Zen cores is valuable. An AMD engineer also added, "We understand the importance of this project to the open-source community and are committed to delivering it as promised." Nonetheless, the primary goal remains achieving full production readiness with the upcoming Zen 6 architecture. The openSIL project promises to enhance Coreboot support and provide developers with full access to low-level system components.

NVIDIA is working with its manufacturing partners to design and build factories that, for the first time, will produce NVIDIA AI supercomputers entirely in the U.S. Together with leading manufacturing partners, the company has commissioned more than a million square feet of manufacturing space to build and test NVIDIA Blackwell chips in Arizona and AI supercomputers in Texas. NVIDIA Blackwell chips have started production at TSMC's chip plants in Phoenix, Arizona. NVIDIA is building supercomputer manufacturing plants in Texas, with Foxconn in Houston and with Wistron in Dallas. Mass production at both plants is expected to ramp up in the next 12-15 months. The AI chip and supercomputer supply chain is complex and demands the most advanced manufacturing, packaging, assembly and test technologies. NVIDIA is partnering with Amkor and SPIL for packaging and testing operations in Arizona.

Within the next four years, NVIDIA plans to produce up to half a trillion dollars of AI infrastructure in the United States through partnerships with TSMC, Foxconn, Wistron, Amkor and SPIL. These world-leading companies are deepening their partnership with NVIDIA, growing their businesses while expanding their global footprint and hardening supply chain resilience. NVIDIA AI supercomputers are the engines of a new type of data center created for the sole purpose of processing artificial intelligence—AI factories that are the infrastructure powering a new AI industry. Tens of "gigawatt AI factories" are expected to be built in the coming years. Manufacturing NVIDIA AI chips and supercomputers for American AI factories is expected to create hundreds of thousands of jobs and drive trillions of dollars in economic security over the coming decades.

Digital Chat Station (DCS)—a tenured leaker of Qualcomm pre-release information—has shared new "Snapdragon 8 Elite Gen 2" chipset details. Earlier today, their Weibo feed was updated with a couple of technological predictions. The announced smartphone chip's "SM8850" identifier was disclosed once again, along with the repeated claim that Qualcomm has selected a 3 nm "N3P" node process. Industry watchdogs expect to see the San Diego-headquartered fabless semiconductor designer introduce its next-generation flagship smartphone SoC in October. The current-gen Snapdragon 8 Elite platform was unveiled last Fall; sporting cutting-edge "Oryon" (aka Phoenix) processor cores and an integrated Adreno 830 graphics solution. DCS reckons that the natural successor will reuse a familiar "2 + 6" core configuration; comprised of two prime "big performance" units, and six "normal" performance-tuned units. An Adreno 840 iGPU was listed as DCS's final point of conjecture.

The incoming "Snapdragon 8 Elite Gen 2" chipset was mentioned in the same sentence as rumored "Pegasus" cores (Phoenix's sequel)—slightly far-fetched rumors from 2024 suggested Qualcomm's upgraded processor architecture being tested at maximum frequencies of 5.0 GHz (on performance cores). As pointed out by Wccftech, Gen 1's performance cores run at 4.47 GHz (by default). In today's follow-up post, DCS claimed that Qualcomm's: "self-developed CPU architecture is now in the second generation, with a performance setting of over 380 W+." Industry watchdogs reckon that the "Snapdragon 8 Elite 2" chip will be capable of recording 3.8+ million point tallies in AnTuTu V10 gauntlets, thanks to the alleged utilization of ArmV9 architecture. DCS theorized that the speculated "SM8850" SoC will support ARM's Scalable Matrix Extension 1 (SME 1) and Scalable Vector Extension 2 (SVE2) instruction sets.

TSMC is reconfiguring its US strategy after a challenging start at its Fab 21 facility near Phoenix, Arizona. The company's initial module took nearly five years to move from groundbreaking to production—far longer than the typical two-year process observed in Taiwan. Early setbacks, including labor issues, rising costs, and cultural differences, slowed progress, but these hurdles have provided valuable lessons. With a clearer understanding of the local construction environment, TSMC plans to speed up future projects. Company executives have identified reliable local contractors and addressed many bottlenecks that once hindered progress. As a result, the Taiwanese maker is gearing up to accelerate construction timelines for its upcoming modules. Notably, TSMC intends to start building its third fab—Fab 21 module 3—this year, aiming for a pace similar to that in Taiwan.

In the current phase, TSMC is finalizing equipment installations for Fab 21 module 1 while laying the groundwork for module 2. The plan is to begin trial production of advanced 3 nm-class chips at module 2 in 2026, with high-volume manufacturing expected to kick off by 2028. The accelerated schedule for module 3 is seen as a pathway to faster production of next-generation chips, including those using the N2-series and A16 process technologies. However, rapid construction is not without risks. A critical concern remains the timely procurement of essential fab tools. Leading suppliers such as ASML and Applied Materials face significant backlogs and capacity constraints, which may delay the delivery of necessary equipment. As TSMC vows to build its US capacity more swiftly, the entire supply chain is watching closely to see if these supply chain challenges can be resolved, ensuring that the company meets its ambitious production timelines while expanding its foothold in the American market.

A recent study by TechInsights is reshaping the narrative around the cost of semiconductor manufacturing in the United States. According to the survey, processing a 300 mm wafer at TSMC's Fab 21 in Phoenix, Arizona, is only about 10% more expensive than similar operations in Taiwan. This insight challenges earlier assumptions based on TSMC founder Morris Chang's comments, which suggested that high fab-building expenses in Arizona made US chip production financially impractical. G. Dan Hutcheson of TechInsights highlighted that the observed cost difference largely reflects the expenses associated with establishing a brand-new facility. "It costs TSMC less than 10% more to process a 300 mm wafer in Arizona than the same wafer made in Taiwan," he explained. The initial higher costs stem from constructing a fab in an unfamiliar market with a new, sometimes unskilled workforce—a scenario not typical for mature manufacturing sites.

A significant portion of the wafer production cost is driven by equipment, which accounts for well over two-thirds of the total expenses. Leading equipment providers like ASML, Applied Materials, and Lam Research charge similar prices globally, effectively neutralizing geographic disparities. Although US labor costs are higher than in Taiwan, the heavy automation in modern fabs means that labor represents less than 2% of the overall cost. Additional logistics for Fab 21, including the return of wafers to Taiwan for dicing, testing, and packaging, add complexity but only minimally affect the overall expense. With plans to expand domestic packaging capabilities, TSMC's approach is proving to be strategically sound. This fresh perspective suggests that the apparent high cost of US fab construction has been exaggerated. TSMC's $100B investment in American semiconductor manufacturing reflects a calculated decision informed by detailed cost analysis—demonstrating that location-based differences become less significant when the equipment dominates expenses.

AMD's openSIL project, aimed towards open CPU silicon initialization code, continues progressing despite a slight delay in its development timeline. The initiative, which will eventually replace the current AGESA system across AMD's client and server processors, received a new update. The company initially targeted the end of 2024 to release proof-of-concept code for Phoenix client SoCs and Turin server hardware. However, as we move through the first quarter of 2025, AMD has acknowledged a slight deviation from this schedule. In a recent statement, AMD representatives assured the developer community that work continues steadily on both Phoenix and Turin proof-of-concept releases.

"We are hard at work preparing the Phoenix and Turin POC's for public release," stated an AMD representative, emphasizing that these releases will serve as sample code previewing future production-worthy implementations. The company clarified that these initial releases are not intended for production environments. The delay has minimal impact on AMD's plan, as the primary goal remains focused on achieving full production readiness with the upcoming Zen 6 architecture. The openSIL project promises to enhance Coreboot support and provide developers with full access to low-level system components. Though limited to select reference motherboards, the proof-of-concept releases will serve as the first milestones in AMD's journey toward more open hardware solutions.

TSMC's new semiconductor manufacturing facility in Phoenix, Arizona, will face production costs approximately 30% higher than its Taiwan-based operations when it begins mass production in early 2025. The increased expenses stem from higher tariffs and transportation costs associated with importing necessary materials from Taiwan. The Arizona facility will start producing 10,000 12-inch wafers monthly using a 4 nm node, with plans to double output to 20,000 wafers at full capacity. Four major technology companies—Apple, NVIDIA, AMD, and Qualcomm—have committed to purchasing chips from the plant for their AI and high-performance computing needs. The 445-hectare facility highlights ongoing challenges in America's semiconductor industry. Despite the aim to strengthen domestic chip manufacturing, the plant must import materials from Taiwan to maintain production quality, revealing gaps in the US semiconductor supply chain.

This overseas dependency drives up operational costs significantly. While TSMC's investment marks an essential step in rebuilding domestic capacity, the substantial cost difference between US and Taiwanese production raises questions about long-term viability. TSMC has already begun trial production at the site and plans to expand operations with additional phases. The company's Phase 2 facility is completed, and equipment is being installed, while future expansions aim to produce 2 nm chips by 2028. However, unless the cost gap narrows, the higher production expenses could impact the plant's competitiveness in the global semiconductor market, even competing with its own Taiwanese facilities, where customers could decide to use Taiwanese fabs due to lower costs. Meanwhile, TSMC continues to expand its Taiwan operations, with plans to build new 2 nm facilities in Kaohsiung's Science Park starting next year.

TSMC is reportedly negotiating with NVIDIA to manufacture advanced "Blackwell" GPUs in its Arizona facility. First reported by Reuters, this partnership could mark another major shift in AI chip production toward US soil. The discussion centers around TSMC's Fab 21 in Phoenix, Arizona, specializing in 4 nm and 5 nm chip production. NVIDIA's Blackwell GPUs utilize TSMC's 4NP process technology, making the Arizona facility a technically viable production site. However, the proposed arrangement faces several logistical challenges. A key issue is the absence of advanced packaging facilities in the United States. There is Amkor that planned to do advanced packaging, but it's only scheduled to begin packaging in 2027. TSMC's sophisticated CoWoS packaging technology is currently available only in Taiwan. This means that chips manufactured in Arizona would need to be shipped back to Taiwan for final assembly, potentially increasing production costs.

While alternative solutions exist, such as redesigning the chips to use Intel's packaging technology or focusing on gaming GPU production in Arizona, these options present their own complications. Intel's packaging methods would likely increase costs, and the current absence of graphics card manufacturing infrastructure in the US makes domestic gaming GPU production less practical. Both TSMC and NVIDIA have declined to comment on the ongoing negotiations, as this is confidential information unknown to the public. Interestingly, TSMC's Arizona facility has already attracted a few more US firms for domestic manufacturing, like Apple, rumored to manufacture its A16 Bionic chip and AMD with high-performance designs, likely either EPYC or Instinct MI chips.

The American semiconductor landscape reached a significant milestone as TSMC's new Arizona manufacturing facility demonstrated remarkable production efficiency, exceeding its Taiwanese counterparts by 4% in yield rates. This achievement, revealed at a recent industry webinar by the company's US division chief, represents a major step forward in America's push to strengthen domestic chip manufacturing capabilities. Since initiating its 4 nm node production operations this spring, the Phoenix-based facility has demonstrated impressive technical proficiency, achieving production standards that match and surpass TSMC's established Taiwanese facilities. The project, backed by substantial federal support, including $11.6 billion in combined grants and loans plus significant tax incentives, aims to establish three cutting-edge manufacturing plants in Arizona.

The company's global leadership praised the facility's performance, noting its strategic importance in demonstrating TSMC's ability to maintain exceptional manufacturing standards across international locations. This success carries particular weight given the project's earlier hurdles, which included workforce challenges and timeline adjustments that shifted the entire production schedule by approximately one year. This development gains additional significance against industry-wide challenges, particularly as competitors like Intel and Samsung face operational and financial obstacles. The semiconductor giant's plans now extend to potential further expansion, with the Phoenix site capable of hosting up to six manufacturing facilities. Future growth prospects could be enhanced by proposed additional government initiatives supporting domestic chip production.

The second generation of AMD Ryzen Z-series processors for handheld gaming consoles, will be led by the Ryzen Z2 Extreme. There will also be an affordable Ryzen Z2 (non-Extreme). We've known for some time that the Z2 Extreme is based on the 4 nm "Strix Point" monolithic silicon, with some optimization (the highest bins to facilitate the best energy efficiency); but now we have a few more details thanks to a leak by Golden Pig Upgrade. AMD's engineering effort with the Z2 Extreme will be to give the console the most generational performance uplift from the iGPU, rather than the CPU.

The "Strix Point" silicon features a significantly updated iGPU from the previous-generation "Phoenix." It's based on the more efficient RDNA 3.5 graphics architecture, which is better optimized for LPDDR5 memory; and comes with 16 compute units (CU), compared to 12 on the "Phoenix." The Ryzen Z2 Extreme will come with all 16 CU enabled. The CPU is where some interesting changes are planned. The "Strix Point" silicon features a dual-CCX CPU, one of these contains four "Zen 5" CPU cores sharing a 16 MB L3 cache, while the other features eight "Zen 5c" cores sharing an 8 MB L3 cache. For the Ryzen Z2 Extreme, AMD is going with an odd 3+5 core configuration. What this means is that the Ryzen Z2 Extreme will have 3 "Zen 5" cores, and 5 "Zen 5c" cores. The L3 cache on the CCX with "Zen 5" cores has been reduced to 8 MB in size. On paper, this is still an 8-core/16-thread CPU with 16 MB of L3 cache (same as "Phoenix,") but now you know that there's more going on.

iiyama is proud to unveil the 27" G-Master GB2795HSU-B1 Gold Phoenix, a high-performance gaming monitor specifically designed for esports enthusiasts and professional gamers. Designed to give competitive players the edge they need in the most intense gaming environments, the monitor offers an impressive 280 Hz refresh rate and a 0.2 ms response time, making it one of the fastest monitors yet in the G-Master portfolio.

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TSMC has reportedly managed to produce yields at its Arizona facility that are on par with yields back home in Taiwan, making its expansion efforts successful. According to Bloomberg, TSMC did a trial production, a multi-month effort, to produce N4 node wafers with low defect rates. With wafers now in TSMC's labs for testing, it is reported that Arizona facility yields have achieved parity with their Taiwanese facilities back home. This indicates that TSMC's efforts to expand in the US are so far considered a success, as advanced chipmaking is a very complex process that is only done by a few makers and in very few locations. With TSMC expanding in the US now and proving that its technology can work on US soil, the company has a green light to start volume production in the first half of 2025.

However, this is only the beginning of TSMC's Arizona expansion. The Taiwanese giant plans to have a second fab operational by 2028 and produce 2 nm and 3 nm chips in the state. Additionally, there will be a third facility for 2 nm and more advanced nodes in Phoenix, bringing the total value of TSMC's US expansion efforts to $65 billion, with $6.6 billion from the CHIPS Act grants and $5 billion in loans from the US government. If upcoming fabs follow the lead of the first facility, US-based production needs will possibly be satisfied.

TechPowerUp has released version 2.60.0 of GPU-Z, a popular graphics sub-system information, monitoring, and diagnostic utility. This latest update brings significant enhancements, including full support for the Arm64 architecture and Qualcomm Snapdragon X Elite GPUs. The release also adds support for AMD Zen 5 CPU temperature monitoring and a wide range of new GPUs from NVIDIA, AMD, and Intel. Notable additions include the NVIDIA 4070 Ti Super (AD102), RTX 4070 (AD103), RTX 4060 Ti (AD104), RTX 4060 (AD106), as well as AMD Zen 5 (Strix Point and Granite Ridge), and Intel Raptor Lake U SKUs and Meteor Lake Intel Arc Graphics.

In addition to expanded hardware support, GPU-Z 2.60.0 addresses several important issues. The update fixes NVIDIA driver version reporting for some pre-2015 versions, resolves an installer problem that prevented closing running instances of GPU-Z, and corrects the "0 MHz" memory clock display on certain AMD RDNA GPUs without overclocking support. Other improvements include a small handle leak fix, added support for the Monster Notebook subvendor ID, and compatibility with new VMWare virtual GPU IDs. The installer now requires Windows 7 or newer, with appropriate messaging for unsupported systems. Users can download the latest version of TechPowerUp GPU-Z from the official TechPowerUp website to access these new features and improvements.

DOWNLOAD: TechPowerUp GPU-Z 2.60.0