Monday, April 14th 2025

Intel's 18A Node Outperforms TSMC N2 and Samsung SF2 in 2 nm Performance Class
Intel's 18A node isn't all about yields and density (which are still very important factors) but also performance. According to Taiwanese media 3C News, citing TechInsights research and calculations, the new leader of node performance is Intel 18A. On a custom scale used by TechInsights, Intel 18A gets a 2.53 score, while the performance score of TSMC N2 is 2.27, and the performance score of Samsung SF2 is 2.19. This is all among two nm-class nodes, where Intel leads the category. Being the first node with a Backside Power Delivery Network (BSPDN), it will appear in the Panther Lake CPUs in late 2025 for testing and early 2026 for shipments. This new power architecture boosts layout efficiency and component utilization by 5-10%, lowers interconnect resistance, and enhances ISO power performance by up to 4%, thanks to a significant drop in intrinsic resistance versus traditional front‑end power routing. Relative to its predecessor, Intel 3, the 18A process delivers a 15% improvement in performance per watt and packs 30% more transistors into the same area.
Featuring RibbonFET design, it has entered risk production. According to Intel, "This final stage is about stress-testing volume manufacturing before scaling up to high volume in the second half of 2025." When it comes to other aspects like SRAM density, high‑performance SRAM cells shrank from 0.03 µm² in Intel 3 to 0.023 µm² in Intel 18A, while high‑density cells contracted to 0.021 µm², reflecting scaling factors of 0.77 and 0.88 respectively and defying previous assumptions that SRAM scaling had plateaued. Intel's innovative "around‑the‑array" PowerVia approach addresses voltage drops and interference by routing power vias to I/O, control, and decoder circuits, freeing up the bit‑cell area from frontal power supplies. The result is a 38.1 Mbit/mm² macro bit density, positioning Intel to rival TSMC's N2. All this, combined with BSPDN, is shaping up a powerful node. We can't wait to get our hands on some 18A silicon in the future and run it through our labs for testing.
Source:
3C News
Featuring RibbonFET design, it has entered risk production. According to Intel, "This final stage is about stress-testing volume manufacturing before scaling up to high volume in the second half of 2025." When it comes to other aspects like SRAM density, high‑performance SRAM cells shrank from 0.03 µm² in Intel 3 to 0.023 µm² in Intel 18A, while high‑density cells contracted to 0.021 µm², reflecting scaling factors of 0.77 and 0.88 respectively and defying previous assumptions that SRAM scaling had plateaued. Intel's innovative "around‑the‑array" PowerVia approach addresses voltage drops and interference by routing power vias to I/O, control, and decoder circuits, freeing up the bit‑cell area from frontal power supplies. The result is a 38.1 Mbit/mm² macro bit density, positioning Intel to rival TSMC's N2. All this, combined with BSPDN, is shaping up a powerful node. We can't wait to get our hands on some 18A silicon in the future and run it through our labs for testing.
36 Comments on Intel's 18A Node Outperforms TSMC N2 and Samsung SF2 in 2 nm Performance Class
They have had a few other hopes in the past, but it turned out that they continued to lose, gradually, market share across all PC and data center segments in recent years. That's your translation.
However, while everyone in this thread talks about power/performance/area and perhaps yields, you're the only one who has mentioned cost. This matters more than ever before as the price per transistor is probably going up on 2nm-class nodes, not down, compared to previous nodes. These nodes will be of interest to those who need, and can pay for, density. Server CPUs and AI accelerators rather than desktop and mobile chips.
Keep in mind 18A isn't just a slight density increase, it's new technology with back side power delivery and a new gate design. The only way keeping 20A alive would have made sense was as a 3rd party node, which obviously no one showed interest in. It was smart to cancel 20A and go all in with 18A.
There were rumors that lower tiers of Arrow Lake would be made on 20A while high end was TSMC which would alleviate the problem I described above. This however did not happen, so I do not believe 20A was viable and instead was a huge loss (R&D for the node itself and potential sales of high volume products) for Intel.
Intel originally promised 18A would be "manufacturing ready" by the end of last year, but it entered "risk production" just recently this year, so it's a little behind. (However, it does appear to be ahead of TSMC's N2 schedule by a good bit.) But when 20A was canceled, Intel claimed it was because 18A showed "early success". How can 18A be 4 months behind schedule if it's showing "early success?"
The early success statement related to where they were in the over all process is just disconnected with the actual calendar. Both statements are "true" but don't hold the same meaning as a calendar statement would.