A Computer GuyI went the quirky SATA route with ANS-9010 and can tell you if you didn't run it with ECC ram or using the on-chip ECC function with regular ram your data will get corrupted within minutes. Of course those were DDR2 days.

rhqqI have one, what's more - I still use it from time to time. non-ecc memory, 8x 4GB sticks. I don't recall having data corruption issues...

AnotherReaderCXL latency is higher than a remote socket's latency in a two socket system. The table below, adapted from the linked paper, compares locally attached and remotely attached CXL latency to local and cross-socket DRAM latency in two and eight socket systems from the Skylake X, Sapphire Rapids and Emerald Rapids generations.

			Local	Local	+NUMA	+NUMA
CPU	DDR Type	Size (GB)	Lat (ns)	BW (GB /s)	Lat (ns)	BW (GB /s)	L1D-L2-L3
SPR2S	16×DDR5	256	114	218	191	97	48KB-2MB-60MB
EMR2S	16×DDR5	256	111	246	193	120	48KB-2MB-160MB
SKX2S	16×DDR4	192	90	52	140	32	32KB-1MB-13.8MB
SKX8S	16×DDR4	384	81	109	411	7	32KB-1MB-38.5MB
CXL Configuration	DDR Type	Size (GB)	Lat (ns)	BW (GB /s)	Lat (ns)	BW (GB /s)	Type, CXL-Spec
CXL-A	2×DDR4	128	214	24	375	14	ASIC, CXL1.1, ×8
CXL-B	2×DDR5	128	271	22	473	13	ASIC, CXL1.1, ×8
CXL-C	2×DDR4	16	394	18	621	14	FPGA, CXL1.1, ×8
CXL-D	4×DDR5	768	239	52	333	14	ASIC, CXL1.1, ×16

Table 1: Experimental platform. “Local” refers to the performance measured by CPUs on the same socket while “+NUMA” indicates memory access from a remote socket.

The authors of the previously referenced paper presented at ASPLOS 2025 (link to PDF) where the DRAM configuration was different and the number of channels were included in the table. I have adapted the table below from the newer paper.

			Local	Local	Remote	Remote
Server	# of channels	Size (GB)	Latency (ns)	Bandwidth (GB/s)	Latency (ns)	Bandwidth (GB/s)	# cores	Frequency (GHz)	L1D-L2-L3
SPR2S	8xDDR5	128	114	218	191	97	32	2.1	48KB-2MB-60MB
EMR2S	8×DDR5	128	111	246	193	120	32	2.1	48KB-2MB-160MB
EMR2S	8×DDR5	1536	117	236	212	119	52	2.3	48KB-2MB-260MB
SKX2S	6×DDR4	96	90	52	140	32	10	2.2	32KB-1MB-13.8MB
SKX8S	6×DDR4	48	81	109	410	7	28	2.5	32KB-1MB-38.5MB
CXL Configuration	# of channels	Size (GB)	Latency (ns)	Bandwidth (GB/s)	Latency (ns)	Bandwidth (GB/s)	Type	CXL-Spec	Server
CXL-A	2×DDR4	128	214	24	375	14	ASIC	CXL 1.1×8	SPR2S/EMR2S
CXL-B	1×DDR5	128	271	22	473	13	ASIC	CXL 1.1×8	SPR2S/EMR2S
CXL-C	2×DDR4	16	394	18	621	14	FPGA	CXL 1.1×8	SPR2S/EMR2S
CXL-D	2×DDR5	756	239	52	333	14	ASIC	CXL 1.1×16	EMR2S

The idea behind CXL was that DRAM from older systems could be reused in newer systems to expand capacity beyond the usual maximum. Currently, 128 GB DDR4 RDIMMs are significantly cheaper than 128 GB DDR5 RDIMMs so using those to expand the capacity of a DDR5 system would save quite a bit of money.

A Computer GuyWould such things be good for VRAM Cache?


I've said this before. It would be awesome if AMD would allow some kind of mode to configure the cache for general purpose use. Not necessarily as a ram disk but for example games or drivers that could take advantage of very high speed read/write access to data structures. I disagree with the article stating that the current cache capacity isn't useful. 96MB to 128MB is a ton of useful memory.


I can imagine i-ram without ecc must have been a disaster. I went the quirky SATA route with ANS-9010 and can tell you if you didn't run it with ECC ram or using the on-chip ECC function with regular ram your data will get corrupted within minutes. Of course those were DDR2 days.