AMD Ryzen 7000 series and Ryzen 9000 series processors are limited in how fast their memory can be clocked when compared to Intel's DDR5 platforms

btarunrAMD at Computex announced the new EXPO Ultra Low Latency memory OC profile standard (EXPO-ULL). This is an SPD profile extension, just like Intel XMP and the original EXPO, but is a standard that prescribes extremely tight memory timings for memory speeds typically marketed to AMD systems, such as DDR5-6000 and DDR5-6400. AMD Ryzen 7000 series and Ryzen 9000 series processors are limited in how fast their memory can be clocked when compared to Intel's DDR5 platforms, but there's room to significantly tighten memory timings.

Memory vendors were simply selling their mid-range DDR5-6000 and DDR5-6400 memory with timings typical of those speeds as AMD EXPO products. AMD's intervention sees memory vendors ship DDR5-6000 and DDR5-6400 kits with significantly tightened timings, so there is a tangible performance benefit being offered to PC enthusiasts versus opting for JEDEC DDR5-6000/6400 kits. Memory vendors onboard with the EXPO-ULL program include G.Skill, Kingston, Klevv, Lexar, Team Group, V-Color, and ADATA XPG. AMD provided first-party testing of how EXPO-ULL memory provides an up to 13% increase in FPS versus generic JEDEC memory kits, and average FPS gains of 4%. The company didn't specify a release date, but we could expect EXPO-ULL memory kit launches from the above vendors throughout 2026.

NhonhoSome youtubers report that the EXPO "low latency" profile causes PC crashes.

Hilux SSRGHow is this different than me doing trial and error on cas and timings manually in bios to reach stable low latency, other than paying a premium for the factory to do this?

ir_cowHmm Intersting. I wonder what timings is included in this new profile standard. I'll find out when I get my hands on a kit I guess.

EXPO ULL also targets lower memory latency with reduction of 5 to 7 ns compared with a regular DDR5-6000 kit. This follows earlier EXPO 1.2 references to new profile fields, including ULL Enable, tREFI, tRRDS, tWR and VDDP voltage.

Hilux SSRGHow is this different than me doing trial and error on cas and timings manually in bios to reach stable low latency, other than paying a premium for the factory to do this?

thestryker6Videocardz is reporting this from an earlier leak:

ir_cowI thought that was just EXPO 1.2 spec. If they really are planning on adding tREFi to its own profile, better start including a fan with every kit :)

EatingDirtRAM timings have always been mostly about the silicon lottery.

rv8000Unless you’re pumping more than 1.5vdd/vddq not really. I’ve run multiple kits daily without issues at 6000-6400 with max trefi and no direct cooling to the dimms outside of the cpu cooler pulling air past them.

Also, trefi is the easiest target for performance gains along with trfc, what did you expect them to be tuning to get any real performance benefit to quote :)

WirkoYes, because DRAM chips were designed for servers and OEM PCs, and the design goals were 1.1 V and CL around 16 ns. That's 98% of the market.

ir_cowYour running 256K? unlikely... I'm guessing you're talking about AMD and that 65K soft limit (Because AMD does that kinda of stuff). You can still crash memory at 65K, depends on the density, IC quality and frequency. Congrats on running daily "max" tREFi :)


Exactly. I tell everyone this. JEDEC is most of the market.

rv800065k has been the effective max for AMD. You can crash memory for any number of reasons. Actually working with kits at max trefi on the AM5 platform you’d better understand 65k is fine on ambient when you’re not slamming vdd/vddq. Apologies though, I forget TPU coverage on ram kits doesn’t actually cover in depth timing tuning :)

ir_cowI thought that was just EXPO 1.2 spec. If they really are planning on adding tREFi to its own profile, better start including a fan with every kit :)

Selayax3d exists

WannaBeOCerThat has always been the reality since the original DDR days where we pay a premium for memory from vendors who have binned the ICs to reliably hit high speeds and low latencies. Given that we already have plenty of low latency kits available, it feels like they are just slapping an EXPO ULL badge on the same kits to justify a price hike. My question is whether this actually introduces any meaningful changes like specific tweaks to AGESA or new memory training parameters that make these tight timings more stable or if it is just a new layer of certification that does not actually offer anything beyond those currently available kits.

ir_cowIt would be interesting to see your review and how you were able to NOT produce errors with dual-rank memory without some direct airflow.

www.techpowerup.com/review/origin-code-vortex-ddr5-6000-192-gb-cl26/10.html

All the information is there for you to replicate if you choose to read it.