Intel's push for advanced packaging is reportedly attracting significant attention from external customers to Intel Foundry. However, the company's latest packaging will only begin mass production next year. Intel's Embedded Multi-die Interconnect Bridge (EMIB) enables designers to use 2D, 2.5D, and 3D building blocks to optimize cost, power, and bandwidth at the system level. EMIB is a substrate-embedded silicon bridge that provides localized, high-density die-to-die routing without the cost and area penalty of a full-size silicon interposer. For example, small silicon EMIB bridges—available in variants like EMIB-M with embedded MIM capacitors and EMIB-T with TSVs—offer low-cost, high-density shoreline connections ideal for logic-to-logic and logic-to-HBM interfaces. The EMIB-T variant, which includes TSVs, allows ASICs to gain direct access to power connections, resulting in a massive, multi-kilowatt solution on a single package.

However, this EMIB-T advanced packaging will only enter mass production next year, as Intel is currently ramping up its regular EMIB and Foveros for customers. According to Taiwan's Unimicron, which manufactures PCBs and silicon substrates, Intel's EMIB-T will reach high-volume production in 2027. The company also notes that customers, including ASIC designers like Broadcom and Meta, are considering switching from TSMC's CoWoS packaging to EMIB to reduce costs while maintaining the same benefits and even gaining more features in some areas. The price gap between EMIB-T and CoWoS (presumably CoWoS-L or CoWoS-R) can be as much as 50%, depending on whether an expensive interposer is required. This means that the costs of advanced packaging are passed back to the customer, who can then invest in other production areas.For Intel, this indicates that customers are actively exploring the use of all EMIB variants to scale their silicon. From regular EMIB to EMIB-M and EMIB-T, customers aim to achieve multi-reticle chips packaged with high-bandwidth memory, all on a package that can support such expansion. Intel is attempting to lure customers away from TSMC with better packaging technology. TSMC reportedly faced issues with the CoWoS-L design for NVIDIA's "Vera Rubin." NVIDIA planned to use CoWoS-L for the design and concept that "Rubin Ultra" was based on. However, it is rumored that in a 2+2 die package—meaning four dies in this architecture—TSMC is encountering warping issues. The package, which includes a substrate, is bending in multiple directions, causing the compute dies of "Rubin Ultra" to not make complete contact with the underlying substrate.