If readers recall, a few days ago we reported that TSMC has achieved a milestone of about 20,000 wafers per month on the company's latest 2 nm N2 node. However, the company is now rapidly scaling its high-volume manufacturing, aiming to produce about 100,000 N2 wafers per month by the end of 2026. This gives the company about four months to increase its manufacturing output fivefold. While that might seem impossible, TSMC has been rapidly scaling its manufacturing output over the years, and the latest N2 node is no exception. Currently, the N2 node accounts for only 3% of TSMC's revenue, while the 3 nm node holds 30%, and the 5 nm node secures the top spot at 33%. Even with projected growth in N3 and N5 consumption, increasing revenue fivefold would mean the N2 node would represent more than 10% of the company's overall revenue share.

Meanwhile, the demand for its 3 nm N3 family of nodes is still strong. Reportedly, TSMC's customers, including NVIDIA, AMD, Broadcom, and many others, have pushed the total monthly wafer output of the N3 node to 180,000 units, exceeding the company's internal targets. While TSMC hoped to achieve this number in the fourth quarter of 2026, demand has pushed production capacity to its limits, prompting TSMC to consider additional expansion plans for this node.This doesn't mean the N2 node is underperforming. Recently, the company confirmed that the N2 node has four times the number of tape-outs compared to its previous leading-edge 3 nm N3 node. With GAAFET technology, TSMC's N2 delivers up to a 15% performance increase at the same power level or up to a 30% power reduction at the same speed. This has led to four times the number of customers doing tape-outs, including AMD with its EPYC "Venice" server CPUs, Apple with its A20 Pro chips for the iPhone 18 Pro series, and many others. Even though the N2 ramp currently accounts for a small portion of revenue and wafer output, the majority of the business is gradually heading in that direction.