Infineon Technologies AG (FSE: IFX / OTCQX: IFNNY) has successfully processed 300-millimeter silicon carbide wafers into functional power devices at its fab in Villach, Austria. Infineon is the first company to pioneer this innovation milestone in a full-scale semiconductor fab environment. It was realized by utilizing existing silicon (Si) manufacturing equipment. This early achievement of functional power devices reflects Infineon's strong focus on providing customers with a comprehensive portfolio of high-performance SiC power semiconductors and ensuring long-term supply. Chip production on 300 mm wafers is technologically more advanced and significantly more efficient than 200 mm wafers, since the larger wafer diameter offers 2.3 times more chips per wafer.

The SEMI Silicon Manufacturers Group (SMG) reported today, in its quarterly analysis of the silicon wafer industry, that worldwide silicon wafer shipments increased 13.4% year-on-year to 3,756 million square inches (MSI) from the 3,313 MSI recorded during the same quarter of 2025. Shipments increased 5.1% quarter-over-quarter from the 3,573 MSI recorded during the second quarter of 2026.

"Silicon wafer shipments increased in the third quarter, supported by strong AI-related demand and improving industrial demand," said Masatsugu Miura, Chairman of SEMI SMG and General Manager of Sales & Marketing Department of Sales & Marketing Division at SUMCO Corporation. "AI-related demand continued to broaden beyond advanced logic and memory to include power devices and photonics. Industrial demand strengthened, supported by robotics, AI server power supplies and improving demand for general-purpose industrial semiconductors. Bonding and advanced packaging applications also continued to support demand for 300 mm polished wafers."

Intel is moving some manufacturing capacity away from consumer chips to keep up with demand for its Xeon server processors. During its Q3 2026 earnings call, the company said it will convert some Intel 18A resources at its Oregon facilities to Intel 3, the node behind Xeon 6 "Granite Rapids." According to CFO Dave Zinsner, those 18A wafers "are generally going to build Panther Lake products." Zinsner also indicated that weaker PC demand gives Intel room to make the switch, as the company expects the PC slowdown to last at least through the first half of next year. CEO Lip-Bu Tan said the added Intel 3 capacity should be in production in the second half of 2027.

Intel CEO Lip-Bu TanThe industry continues to navigate one of the most significant supply shortages in the history, driven by the unprecedented demand for Super Intelligence. Against this backdrop, I am pleased by the progress we made growing our server supply in Q3. I'm mindful about the ongoing challenges we face in the future quarters to keep pace with the server demand.

TSMC is reportedly considering raising prices for its CoWoS (Chip on Wafer on Substrate) advanced packaging by as much as 20%, according to supply chain sources cited by Taiwan's Commercial Times. Foundries and outsourced packaging firms are apparently weighing another round of 10% to 20% increases, as CoWoS demand has spread beyond AI GPUs to server CPUs and custom ASICs, leaving a growing backlog of unfilled orders. TSMC hasn't confirmed anything yet.

Testing is turning into a bottleneck of its own. Nomura estimates, via Seoul Economic Daily, that NVIDIA's Blackwell takes roughly four times longer than Hopper in final testing, while Rubin could need seven times as long. Packages keep growing too, with TSMC already mass producing CoWoS-L at 5.5 times the reticle limit. Tool lead times have reportedly stretched from three to six months to as long as eight months. TSMC, which usually negotiates for discounts or extra features, apparently placed this year's equipment orders at existing prices instead, which says a lot about how tight things are.

Micron is actively working on bringing its next-generation G11 NAND Flash technology to production, as the company has announced that G11 will be its first 3D NAND Flash. With the current G9 technology shipping across Micron's product portfolio, the company has created NAND Flash storage modules using over 200 layers of scaling. However, as the current technology reaches its limitations, the next phase involves exploring vertical stacking. With G11, Micron aims to use wafer-on-wafer 3D NAND stacking to double the capacity of NAND modules. Micron is now officially following in the footsteps of Chinese NAND giant YMTC, which has been making 3D stacked NAND for some time using Xtacking technology.

This is achieved by splitting each wafer into separate components. One is designed as a memory cell wafer, while the other contains peripheral logic circuits. These are combined using hybrid bonding technology in wafer-to-wafer stacking. Hybrid bonding creates a permanent bond between two silicon chips using embedded metal bumps that fuse together to form a single chip. Multiple dies or entire silicon wafers can be connected by stacking the back ends of two chips together. In this way, Micron plans to ship 400-layer NAND in the second half of 2027, which is less than a year away, and we are about to see more commercialization of 3D silicon.

TSMC has reportedly started expanding its manufacturing capacity as demand continues to outpace supply. According to a recent report from UDN, TSMC aims to increase its 2 nm manufacturing capacity at the N2 node, targeting an output of about 120,000 wafers per month by the end of 2026. This represents a 20% increase from the early August target of 100,000 wafers per month by the end of the year, indicating strong customer interest in the latest silicon technology. Even in the early stages, the company confirmed that the N2 node has four times the number of tape-outs compared to its previous leading-edge 3 nm N3 node. With the ramp-up of N2 production underway, the 20% increase suggests that customers are seeking more capacity, even as TSMC continues to scale production, indicating that demand isn't slowing down anytime soon.

At the end of the second quarter of 2026, the N2 node accounted for only 3% of TSMC's revenue, while the 3 nm node held 30%, and the 5 nm node secured the top spot at 33%. However, as we approach the end of Q3, we should see a significant shift in these figures, strongly favoring the N2 node. Until official data is released, we can't be certain of N2's exact revenue contribution, but it is expected to increase significantly based on several factors.

SK hynix expects the current memory shortage to persist through the end of 2030, with no clear signs of a slowdown yet, according to CEO Kwak Noh-Jung. Speaking after the company's groundbreaking ceremony for its new Indiana packaging facility, Kwak said any eventual slowdown would likely be the result of a gradual easing rather than the sharp price crashes memory markets have previously seen, per Reuters. SK hynix had previously flagged tight supply lasting through 2028 for commodity DRAM, so this latest comment pushes that prediction out further.

Kwak's reasoning is that memory products have moved away from being purely commodity parts. AI-driven demand has pushed customers toward customized DRAM and HBM configurations, which makes future demand easier for manufacturers to forecast and less prone to the abrupt oversupply swings that caused previous crashes.

Lam Research Corp. (NASDAQ: LRCX) today announced that it intends to invest more than $3 billion over the next five years to expand its global research and development (R&D) lab network. The planned multi-site expansion is expected to add infrastructure and capabilities to increase experiment capacity by more than 50%. Lam's R&D approach combines specialized labs worldwide, each purpose-built to accelerate a distinct step of the innovation cycle, with deep customer collaboration that includes locations near customer facilities. Together, Lam's labs operate as an integrated 24/7 network, enabling innovation in parallel and at scale. With this investment, Lam intends to further compress product development cycles for customers, from pathfinding to fab deployment.

"In the AI era, the pace of innovation is relentless, requiring chips with new architectures, different materials, and complex features engineered with nanoscale precision. Our ability to increase velocity throughout the R&D process has become a decisive advantage," said Tim Archer, president and chief executive officer of Lam Research. "We are investing with the intention of staying ahead of what our customers need, further strengthening our global innovation engine to deliver the next generation of semiconductor breakthroughs."

If readers recall, a few days ago we reported that TSMC has achieved a milestone of about 20,000 wafers per month on the company's latest 2 nm N2 node. However, the company is now rapidly scaling its high-volume manufacturing, aiming to produce about 100,000 N2 wafers per month by the end of 2026. This gives the company about four months to increase its manufacturing output fivefold. While that might seem impossible, TSMC has been rapidly scaling its manufacturing output over the years, and the latest N2 node is no exception. Currently, the N2 node accounts for only 3% of TSMC's revenue, while the 3 nm node holds 30%, and the 5 nm node secures the top spot at 33%. Even with projected growth in N3 and N5 consumption, increasing revenue fivefold would mean the N2 node would represent more than 10% of the company's overall revenue share.

Meanwhile, the demand for its 3 nm N3 family of nodes is still strong. Reportedly, TSMC's customers, including NVIDIA, AMD, Broadcom, and many others, have pushed the total monthly wafer output of the N3 node to 180,000 units, exceeding the company's internal targets. While TSMC hoped to achieve this number in the fourth quarter of 2026, demand has pushed production capacity to its limits, prompting TSMC to consider additional expansion plans for this node.

The SEMI Silicon Manufacturers Group (SMG) reported today, in its quarterly analysis of the silicon wafer industry, that worldwide silicon wafer shipments increased 7.4% year-on-year to 3,573 million square inches (MSI) from the 3,327 MSI recorded during the same quarter of 2025. Shipments increased 9.1% quarter-over-quarter from the 3,275 MSI recorded during the first quarter of 2026.

"Silicon wafer shipments maintained steady growth in the second quarter, driven by strong and increasing AI-related demand beyond advanced logic and memory to include power devices, photonics, and other markets," said Ginji Yada, Chairman of SEMI SMG and Managing Executive Officer, General Manager, Sales and Marketing Division at SUMCO Corporation. "In addition, industrial and automotive demand is recovering, while memory price pressures are contributing to constrained PC and smartphone demand. Device manufacturers are investing heavily in capacity expansion, and silicon wafer demand growth is expected to continue."

TSMC has reportedly reached a new milestone in scaling its 2 nm node high-volume manufacturing, now producing 20,000 wafers per month on the N2 node alone. Manufactured across five fabs in Taiwan, the company currently has only one fab in volume production on the N2 node. This is reportedly Fab 20, which has reached this figure. TSMC began high-volume production of its N2 node in the fourth quarter of 2025. Fast-forward two quarters to today, and the 2 nm node now accounts for only 3% of the company's revenue, while the 3 nm node commands 30%, and the 5 nm node holds the top spot at 33%.

Recently, the company confirmed that the N2 node has four times the number of tape-outs compared to its previous leading-edge 3 nm N3 node. With GAAFET technology, TSMC's N2 delivers up to a 15% performance increase at the same power level or up to a 30% power reduction at the same speed. This has driven four times the number of customers doing tape-outs, including AMD with its EPYC "Venice" server CPUs, Apple with its A20 Pro chips for the iPhone 18 Pro series, and many others. Even though the N2 ramp now accounts for a small portion of revenue and wafer output, the majority of the business is gradually heading in that direction.

Intel has reportedly resolved all yield issues it experienced with its 18A node over the past few months. According to the sell-side equity research firm BlueFin Research Partners, Intel has fixed these yield issues, making the high-volume production of its latest node sustainable from both a manufacturing yield and economic standpoint. Readers may recall that late last year, Intel confirmed that 18A yields were improving by about 7% per month over several months. This trend continued into the launch of the first 18A product, codenamed "Panther Lake," up until today, when the yield issues have reportedly been resolved. For a mature node, this usually means defect rates of D0=0.1 or D0=0.2, and it is likely that Intel has now achieved the lower end of that spectrum with the node advancements and months of 18A high-volume production.

Regarding manufacturing capacity, the report notes that Intel's 18A is produced at two sites: Fab 52 in Phoenix, Arizona, and another in Hillsboro, Oregon. These fabs currently produce about 30,000 wafers per month with the 18A printing. This capacity is currently sufficient for Intel's internal production, such as the "Panther Lake" processors, but additional capacity will be needed for other internal products.

CEA-Leti today announced a major milestone in the evolution of 3D integration for high-performance computing (HPC), advanced smart-vision systems and artificial intelligence (AI), demonstrating a functional test vehicle utilizing die-to-wafer (D2W) hybrid bonding with pitches down to 1 μm. The findings were presented at the Electronic Components and Technology Conference (ECTC) 2026.

As Moore's Law reaches physical limits, the semiconductor industry is increasingly relying on 3D stacking to enhance performance and energy efficiency. This D2W technology addresses a critical bottleneck in AI accelerator design: interconnect density and bandwidth. By vertically stacking device layers with ultra-fine pitches, the technology shortens interconnect paths, significantly increasing data transfer speeds while reducing power consumption.

Breakthrough in chip manufacturing: As part of the European APECS pilot line, researchers at Fraunhofer Institute for Photonic Microsystems IPMS have developed a method that allows different chip components to be fused almost seamlessly into a single unit. By precisely embedding small chiplets into specially structured silicon pockets, Fraunhofer IPMS succeeded in combining the advantages of a compact single chip with the flexibility of modular systems for the first time. This achievement demonstrates the feasibility of quasi-monolithic integration (QMI) and bridges the gap between traditional chip packaging and cutting-edge semiconductor manufacturing.

Growing demands for greater complexity, computing power and system compactness are calling for a radical rethink of semiconductor manufacturing. The vision for future-proof microelectronics is to create systems that are as powerful as a single chip yet offer the flexibility of modular building blocks. Within the APECS pilot line, which focuses on "Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems", Fraunhofer IPMS is pursuing the quasi-monolithic integration (QMI) approach. The aim is to integrate various chip components, such as control electronics, sensors and microelectromechanical systems (MEMS), at the wafer level, while retaining the benefits of a compact single chip.

Global semiconductor materials market revenue increased 6.8% year-over-year to $73.2 billion in 2025, SEMI, reported today in its Materials Market Data Subscription (MMDS). Growth was supported by gains in both the wafer fab materials and packaging materials segments, reflecting higher process complexity, advanced-node demand, and continued investment in high-performance computing and high-bandwidth memory manufacturing.

Wafer fabrication materials revenue increased 5.4% to $45.8 billion. Lithography-related materials, including photomask, photoresist and ancillaries, along with wet chemicals, posted strong double-digit growth as higher process intensity and tighter lithography requirements continued to increase materials consumption.

The SEMI Silicon Manufacturers Group (SMG) reported today, in its quarterly analysis of the silicon wafer industry, that worldwide silicon wafer shipments increased 13.1% year-on-year to 3,275 million square inches (MSI) from the 2,896 MSI recorded during the same quarter of 2025. Sequentially, shipments declined 4.7% quarter-over-quarter from the 3,437 MSI recorded during the fourth quarter of 2025 in line with typical seasonality.

"Silicon wafer demand related to AI data centers continues to be strong, including advanced logic and memory, and also now extending to power management devices," said Ginji Yada, Chairman of SEMI SMG and Managing Executive Officer, General Manager, Sales and Marketing Division at SUMCO Corporation. "Overall, silicon wafer demand has improved, but the recovery is not uniform. Many device companies have noted improvements in the industrial semiconductor segment, and this is creating a more broad-based recovery as wafer inventory is absorbed. Weaker smartphone and PC shipments in the first quarter of this year may show the impact of tighter supply of memory due to AI high bandwidth memory (HBM) allocation decisions."

Wolfspeed, Inc. (NYSE: WOLF), a global leader in silicon carbide technology, today announced that its 300 mm silicon carbide (SiC) technology platform could serve as a foundational materials enabler for advanced AI and high-performance computing (HPC) heterogeneous packaging by the end of this decade.

"As AI workloads continue to increase package size, power density, and integration complexity, we believe new materials foundations will be increasingly important to extend advanced packaging roadmaps," said Elif Balkas, Chief Technology Officer at Wolfspeed. "Our 300 mm silicon carbide platform is designed to align SiC's material advantages with industry-standard manufacturing infrastructure and expand the solution space for next-generation AI and HPC packaging architectures."

Worldwide silicon wafer shipments in 2025 increased 5.8% to 12,973 million square inches (MSI) while wafer revenue slipped 1.2% to $11.4 billion over the same period, the SEMI Silicon Manufacturers Group (SMG) reported in its year-end analysis of the silicon wafer industry.

2025 marks an inflection year for wafer shipments, with silicon MSI resuming growth supported by strong demand for advanced epitaxial wafers in logic and polished wafers for high-bandwidth memory (HBM), driven by AI applications. Softness in wafer revenue is mostly attributed to the slow momentum in traditional semiconductor applications where the demand and pricing environment are yet to improve.

Intel's concluded its Q4 and full-year 2025 earnings call, revealing interesting things about its foundry operations and node selection. When talking about the upcoming 14A node, Intel confirmed that the node is on track for 2027, with yields that are in good shape. However, the bulk of the 14A external capacity Intel will dedicate depends on customers willing to sign manufacturing contracts first, before Intel spends insane amount of funds required to expand manufacturing capacity. Intel CEO Lib-Bu Tan noted "Engagements with potential external customers on Intel 14A are active. We believe customers will begin to make firm supplier decisions starting in the second half of this year and extending into the first half of 2027. We also have the opportunity to provide strong differentiation in advanced packaging, particularly with EMIB and EMIB-T."

Intel CFO David Zinsner has stated "On 14A, Lip-Bu has been very direct with us on all of this. He does not want to spend on capacity on 14A, only spend on the kind of TD spend or R&D spend associated with 14A, even in the fab until we have customers secured. We've talked about the likelihood is our customers on 14A, their window to secure, or for us to secure them will be in the back half of this year and in the first half of next year. And so once visibility improves there, we'll start to unlock the spend on 14A. I can just add a little bit more. I think on the yield improvement, we see 7%, 8% yield improvement per month." Intel has previously mentioned that while there will be a base capacity for internal use, any future expansion for third-party services will depend on customers' willingness to invest capital with Intel Foundry.

Intel Foundry has massive capacity in the United States, with its size surpassing that of TSMC's Arizona campus in terms of production capacity and building space. A CNBC crew visited Intel's Fab 52 in Arizona to explore its operations, uncovering some intriguing details about wafer capacity and future production plans. According to their report, Intel's Fab 52 produces approximately 10,000 wafers per week, totaling over 40,000 wafers per month. These wafers are manufactured using the 18A node, Intel's most advanced design, featuring innovations such as a backside power delivery network and gate-all-around transistors, among others.

Compared to TSMC's facility in Arizona, Intel's manufacturing capacity and node designs are superior. TSMC currently produces about 20,000 wafers per month at the older N5 and N4 nodes, which are 5 nm class, in the Fab 21 Phase 1 stage. Although TSMC plans to expand Fab 21 to increase wafer capacity and introduce more advanced nodes, these advancements will primarily remain in Taiwan, keeping U.S.-based TSMC production a few generations behind. Intel, on the other hand, has a limited number of external partners using its nodes, with the 18A node being primarily for Intel's own products, including the upcoming "Panther Lake" processor, and some future generations.

Interesting developments are unfolding in the world of DRAM and NAND flash, as one of the largest players, SK Hynix, has announced product updates for 2026. The company appears to be following its competitor Samsung by slowing the ramp-up of its next-generation HBM4. Initially, SK Hynix planned to increase its HBM4 capacity in the second quarter of 2026. However, this has been postponed to the third quarter of 2026, as the company plans to expand its HBM4 manufacturing capacity. The delay is due to the high demand for its current HBM3E capacity, necessitating the continued operation of HBM3E manufacturing sites longer than expected. SK Hynix's largest customer for HBM chips, NVIDIA, is reportedly facing challenges with the volume production of "Rubin," delaying the need for HBM4, while the HBM3E-equipped "Blackwell" remains in strong demand.

United Microelectronics Corporation (NYSE: UMC: TWSE: 2303) ("UMC"), a leading global semiconductor foundry, and Polar Semiconductor, LLC ("Polar"), a U.S.-owned and operated foundry specializing in high-voltage, power, and sensor technologies, today announced they have signed a Memorandum of Understanding (MOU) to explore collaboration on delivering scalable U.S.-based 8-inch production of high-quality wafers that are essential across pillar industries including automotive, data centers, consumer electronics, and aerospace & defense.

Under the MOU, Polar and UMC will identify devices for Polar to manufacture at its recently expanded 8-inch facility in Minnesota. By combining Polar's proven manufacturing capabilities with UMC's comprehensive 8-inch technology portfolio and global customer base, this partnership is set to drive growth for both companies while supporting customers' multi-sourcing strategies. In addition, the collaboration will strengthen 8-inch wafer manufacturing in the U.S., contributing to supply chain resilience amid shifting geopolitical dynamics and ensuring a secure domestic supply of power semiconductors critical to automotive, electric grids, robotic manufacturing, data centers, and more.

Intel was presenting at 2025 UBS Global Technology and AI Conference, revealing interesting details about the demand for its "Lunar Lake" and "Arrow Lake" processors. On the question from one of the analysts that some assume Intel isn't selling its new products and there is no demand, Intel's John Pitzer answered "Quite frankly, if we had more Granite wafers, we'd be selling more Granite. If we had more Lunar Lake wafers, we'd be selling more Lunar Lake. If we had more Arrow Lake wafers, we'd be selling more Arrow Lake. And so I think we feel pretty good about where we are in the AI PC transition. And we feel very good about where we are in the initial phase of the Granite ramp, which is our latest generation server part."

This puts an end to the speculation that Intel's products aren't selling well, and the recent Q3 revenue figure of $13.7 billion matches that. Additionally, Intel made comments about its internal and external manufacturing capacity. Intel's "Lunar Lake" and "Arrow Lake" are SoCs that are fully outsourced to TSMC, with Intel performing the packaging. Hence, Intel's limited capacity booked at TSMC is not enough to satisfy the demand. However, starting with "Panther Lake," the wafer supply is getting back in-house as 18A yields mature. All the "Panther Lake" logic dies will be manufactured in-house, compared to 0% of logic dies manufactured in-house for "Arrow Lake" and "Lunar Lake."

TrendForce's latest research shows that demand for NAND Flash stayed strong in November 2025, fueled by AI applications and solid enterprise SSD orders. Meanwhile, suppliers continued to focus on capacity for high-margin enterprise and premium products, while old-node capacity was quickly phased out.

This led to a further tightening of wafer supply, causing November contract prices for mainstream wafers to rise sharply. Monthly average price increases varied from 20% to over 60% across all product categories, with the surge quickly expanding to all density segments.

Just three days ago, NVIDIA and TSMC celebrated the production of the first "Blackwell" GPU at TSMC's Fab 21 complex in Phoenix, Arizona. This marked a significant milestone for both companies, as it signifies the creation of the world's most powerful silicon on U.S. soil. However, the production phase is only part of the story, as the chip benefits not only from an advanced node but also from TSMC's advanced packaging systems. Specifically, the Blackwell family of GPUs utilizes TSMC's Chip on Wafer on Substrate (CoWoS) packaging system.

For CoWoS access, TSMC must send these chips back to the Taiwanese facilities overseas and house the raw die in a CoWoS-S configuration with silicon interposer. This establishes a supply chain dependency on Taiwanese facilities, which remain essential for completing the production of advanced silicon. As a result, the chip isn't entirely manufactured on American soil, indicating that some issues still need to be resolved. TSMC produces NVIDIA's Blackwell chips using a custom 4N 4 nm class node specifically designed for NVIDIA. This die is paired with eight stacks of HBM3E, all housed within a CoWoS-S package.