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Marvell and TSMC Collaborate to Deliver Industry's Most Advanced Data Infrastructure Portfolio on 5nm Tech

Marvell, a leading provider of data infrastructure semiconductor solutions, today announced an extension of their long term partnership with TSMC (TWSE: 2330; NYSE:TSMC), the world's largest dedicated semiconductor foundry, to deliver a comprehensive silicon portfolio for the data infrastructure market leveraging the industry's most advanced 5 nanometer (nm) process technology. Next-generation infrastructure has never been more critical to the global economy. It's what's keeping the world connected, businesses running and information flowing. With this collaboration, Marvell and TSMC are advancing the essential technology underpinning this infrastructure to provide the storage, bandwidth, speed, and intelligence that tomorrow's digital economy demands - with the added customer benefit of significant energy efficiency. Built in partnership with TSMC on the most advanced process technology currently in volume production, Marvell's new 5 nm portfolio will enable leading-edge silicon innovation for the infrastructure market.

Marvell's breakthrough 5 nm portfolio will provide the essential high-performance compute, networking and security technology required to advance infrastructure development for a multitude of end-market applications. Marvell's Ethernet connectivity solutions enable high-performance, low-power network connectivity, optimized for applications that span cloud data centers to the harsh environment of the automotive market. Marvell's OCTEON platform is the industry's leading Arm-based high-performance compute architecture for embedded infrastructure applications targeting a wide variety of wired and wireless networking equipment including switches, routers, secure gateways, firewalls, and network monitoring solutions. OCTEON is the world's most widely deployed data processing unit (DPU) for data-center scale computing and enables a multitude of acceleration and offload capabilities, including Smart NICs and security accelerators. Featuring optimized and customized 5G processing and baseband capabilities, Marvell's OCTEON Fusion platform is pushing the boundaries of wireless network infrastructure.

TSMC Details 3nm N3, 5nm N5, and 3DFabric Technology

TSMC on Monday kicked off a virtual tech symposium, where it announced its new 12 nm N12e node for IoT edge devices, announced the new 3DFabric Technology, and detailed progress on its upcoming 5 nm N5 and 3 nm N3 silicon fabrication nodes. The company maintains that the N5 (5 nm) node offers the benefits of a full node uplift over its current-gen N7 (7 nm), which recently clocked over 1 billion chips shipped. The N5 node incorporates EUV lithography more extensively than N6/N7+, and in comparison to N7 offers 30% better power at the same performance, 15% more performance at the same power, and an 80% increase in logic density. The company has commenced high-volume manufacturing on this node.

2021 will see the introduction and ramp-up of the N5P node, an enhancement of the 5 nm N5 node, offering a 10% improvement in power at the same performance, or 5% increase in performance at the same power. A nodelet of the N5 family of nodes, called N4, could see risk production in Q4 2021. The N4 node is advertised as "4 nm," although the company didn't get into its iso-power/iso-performance specifics over the N5 node. The next major node for TSMC will be the 3 nm N3 node, with massive 25%-30% improvement in power at the same performance, or 10%-15% improvement in performance at same power, compared to N5. It also offers a 70% logic density gain over N5. 3DFabric technology is a new umbrella term for TSMC's CoWoS (chip on wafer on substrate), CoW (chip on wafer), and WoW (wafer on wafer) 3-D packaging innovations, with which it plans to offer packaging innovations that compete with Intel's various new 3D chip packaging technologies on the anvil.

AMD Confirms "Zen 4" on 5nm, Other Interesting Tidbits from Q2-2020 Earnings Call

AMD late Tuesday released its Q2-2020 financial results, which saw the company rake in revenue of $1.93 billion for the quarter, and clock a 26 percent YoY revenue growth. In both its corporate presentation targeted at the financial analysts, and its post-results conference call, AMD revealed a handful interesting bits looking into the near future. Much of the focus of AMD's presentation was in reassuring investors that [unlike Intel] it is promising a stable and predictable roadmap, that nothing has changed on its roadmap, and that it intends to execute everything on time. "Over the past couple of quarters what we've seen is that they see our performance/capability. You can count on us for a consistent roadmap. Milan point important for us, will ensure it ships later this year. Already started engaging people on Zen4/5nm. We feel customers are very open. We feel well positioned," said president and CEO Dr Lisa Su.

For starters, there was yet another confirmation from the CEO that the company will launch the "Zen 3" CPU microarchitecture across both the consumer and data-center segments before year-end, which means both Ryzen and EPYC "Milan" products based on "Zen 3." Also confirmed was the introduction of the RDNA2 graphics architecture across consumer graphics segments, and the debut of the CDNA scalar compute architecture. The company started shipping semi-custom SoCs to both Microsoft and Sony, so they could manufacture their next-generation Xbox Series X and PlayStation 5 game consoles in volumes for the Holiday shopping season. Semi-custom shipments could contribute big to the company's Q3-2020 earnings. CDNA won't play a big role in 2020 for AMD, but there will be more opportunities for the datacenter GPU lineup in 2021, according to the company. CDNA2 debuts next year.

Samsung Expands its Foundry Capacity with A New Production Line in Pyeongtaek

Samsung Electronics Co., Ltd., a world leader in advanced semiconductor technology, today announced plans to boost its foundry capacity at the company's new production line in Pyeongtaek, Korea, to meet growing global demand for cutting-edge extreme ultraviolet (EUV) solutions.

The new foundry line, which will focus on EUV-based 5 nanometer (nm) and below process technology, has just commenced construction this month and is expected to be in full operation in the second half of 2021. It will play a pivotal role as Samsung aims to expand the use of state-of-the-art process technologies across a myriad of current and next generation applications, including 5G, high-performance computing (HPC) and artificial intelligence (AI).

TSMC Building a 5nm Fab in Arizona as the U.S. Government Gets Involved

It has become a matter of national strategy (or pride) to get TSMC to build a cutting-edge silicon fabrication facility on U.S. soil. Hot on the heals of a report in which TSMC denied it has any plans to build a fab in the U.S., we're learning from a Wall Street Journal that the world's largest independent semiconductor manufacturing company, will build a facility in the U.S. after all. Apparently TSMC will build a silicon fabrication facility in the state of Arizona. The fab will manufacture 5 nm-class chips, to begin with.

TSMC got around to drawing up plans to build a stateside facility after the "involvement" of the State- and Commerce Departments of the U.S. Government. The two are involved not just in coaxing TSMC, but also in the specifics of the planning to get them to the Grand Canyon state. The Donald Trump administration made significant national policy changes with manufacturing, in the wake of the COVID-19 pandemic causing significant wait times in getting silicon products from Asia to the US.

Update 01:25 UTC: TSMC made its U.S. fab plans official with an announcement. Press release and additional commentary below.

TSMC Secures Orders from NVIDIA for 7nm and 5nm Chips

TSMC has reportedly secured orders from NVIDIA for chips based on its 7 nm and 5 nm silicon fabrication nodes, sources tell DigiTimes. If true, it could confirm rumors of NVIDIA splitting its next-generation GPU manufacturing between TSMC and Samsung. The Korean semiconductor giant is commencing 5 nm EUV mass production within Q2-2020, and NVIDIA is expected to be one of its customers. NVIDIA is expected to shed light on its next-gen graphics architecture at the GTC 2020 online event held later this month. With its "Turing" architecture approaching six quarters of market presence, it's likely that the decks are being cleared for a new architecture not just in HPC/AI compute product segment, but also GeForce and Quadro consumer graphics cards. Splitting manufacturing between TSMC and Samsung would help NVIDIA disperse any yield issue arriving from either foundry's EUV node, and give it greater bargaining power with both.

Samsung to Commence 5nm EUV Mass-Production in Q2-2020, Develop 3nm GAAFET Node

Samsung in its Q1-2020 financials release disclosed that the company will commence mass production of chips on its cutting-edge 5 nanometer EUV silicon fabrication process within Q2-2020 (that's before July 2020). This is big, as it lends credence to rumors of NVIDIA secretly developing 5 nm GPUs. Suddenly, it's possible that "Ampere," if not "Hopper," is 5 nm EUV-based, as NVIDIA has chosen Samsung to be its foundry partner for next-generation GPUs.

"In the second quarter, the Company aims to expand EUV leadership, beginning with the start of mass production of 5 nm products, while closely monitoring the uncertain market situation caused by COVID-19," the company states in the release. Samsung also announced that following commencement of mass production on 5 nm, further development of GAAFET (gate all-around FET) 3 nanometer silicon fabrication process will get underway. The company appears to be erring on the side of caution with its forward-looking statements, though. Much of what Samsung does will be dictated by the impact of COVID-19 on the supply chain and market.

Huawei's Loss AMD's Gain, TSMC Develops Special 5nm Node

With Mainland Chinese tech giant Huawei being effectively cut off from contracting Taiwanese TSMC to manufacture its next-generation HiSilicon 5G mobile SoCs, and NVIDIA switching to Samsung for its next-generation GPUs, TSMC is looking to hold on to large high-volume customers besides Apple and Qualcomm, so as to not let them dictate pricing. AMD is at the receiving end of the newfound affection, with the semiconductor firm reportedly developing a new refinement of its 5 nm node specially for AMD, possibly to make Sunnyvale lock in on TSMC for its future chip architectures. A ChainNews report decoded by @chiakokhua sheds light on this development.

AMD is developing its "Zen 4" CPU microarchitecture for a 5 nm-class silicon fabrication node, although the company doesn't appear to have zeroed in on a node for its RDNA3 graphics architecture and CDNA2 scalar compute architecture. In its recent public reveal of the two, AMD chose not to specify the foundry node for the two, which come out roughly around the same time as "Zen 4." It wouldn't be far fetched to predict that AMD and TSMC were waiting on certainty for the new 5 nm-class node's development. There are no technical details of this new node. AMD's demand for TSMC is expected to be at least 20,000 12-inch wafers per month.

TSMC N5P 5nm Node Offers 84-87% Transistor Density Gain Over Current 7nm Node

A WikiChip analysis of TSMC's next-generation 5 nanometer N5P silicon fabrication node estimates a massive 84-87% increase in transistor densities on offer compared to the company's first commercial 7 nm-class node, the N7 (7 nm DUV). The report estimates an 87% transistor-density increase, even though TSMC's own figure is slightly modest, at 84%. TSMC N5P node is expected to commence production later this year. Its precursor, TSMC N5, began risk production earlier this year, with production on the node commencing in April or May, unless derailed by the COVID-19 pandemic. The N5P node provides transistor densities of an estimated 171.3 million transistors per mm² die area, compared to 91.2 mTr/mm² of N7. Apple is expected to be the node's biggest customer in 2020, with the company building its A14-series SoC on it.

Samsung Announces Breakthrough in Building Blocks of 3nm Circuits, Updates Roadmap

Samsung Electronics Co., Ltd., a world leader in advanced semiconductor technology, today announced its ongoing commitment to foundry innovation and service at the Samsung Foundry Forum 2019 USA, providing the silicon community with wide-ranging updates on technology advances that support the most demanding applications of today and tomorrow.

The event, held today in Santa Clara, California, features top Samsung executives and industry experts reviewing progress on semiconductor technologies and foundry platform solutions that enable developments in artificial intelligence (AI), machine learning, 5G networking, automotive, the Internet of Things (IoT), advanced data centers and many other domains.

Intel Courting Samsung to Manufacture Xe GPUs?

Intel's Xe discrete GPU project head Raja Koduri recently visited a Samsung Electronics silicon fabrication facility in Korea at the backdrop of the company's major 5 nm EUV announcement. This sparks speculation that Koduri could be exploring Samsung's portfolio of sub-10 nm contract-manufacturing offerings to mass-produce Xe discrete GPUs. Intel's own foundry business is reeling with mounting pressure from the company's main breadwinner, the client and enterprise processor businesses, to get its 10 nm node on the road. Koduri's GPU would need to leverage higher transistor densities than what Intel's 10 nm could offer, given that rival AMD is already implementing 7 nm, and NVIDIA is expected to go sub-10 nm with its future generation of GPUs.

Samsung Successfully Completes 5nm EUV Development

Samsung Electronics Co., Ltd., a world leader in advanced semiconductor technology, today announced that its 5-nanometer (nm) FinFET process technology is complete in its development and is now ready for customers' samples. By adding another cutting-edge node to its extreme ultraviolet (EUV)-based process offerings, Samsung is proving once again its leadership in the advanced foundry market.

Compared to 7 nm, Samsung's 5 nm FinFET process technology provides up to a 25 percent increase in logic area efficiency with 20 percent lower power consumption or 10 percent higher performance as a result of process improvement to enable us to have more innovative standard cell architecture. In addition to power performance area (PPA) improvements from 7 nm to 5 nm, customers can fully leverage Samsung's highly sophisticated EUV technology. Like its predecessor, 5 nm uses EUV lithography in metal layer patterning and reduces mask layers while providing better fidelity.

TSMC is Ramping Up 7nm Production, 5nm Next Year

At their technology symposium in Taipei, TSMC CEO CC Wei has made remarks, dismissing speculation that their 7 nanometer yield rate was not as good as expected. Rather the company is ramping up production capacity for 7 nm quickly, up 9% from 10.5 million wafers in 2017, to 12 million wafers in 2018. They plan to tape out more than 50 chip designs in 2018, with the majority of the tape outs for AI, GPU and crypto applications, followed by 5G and application processors.

Most of their orders for the 7 nanometer node come from big players like AMD, Bitmain, NVIDIA and Qualcomm. Apple's A12 processor for upcoming iPhones is also a major driver for TSMC's 7 nanometer growth. These orders will be fulfilled in early 2019, so it'll be a bit longer before we have 7 nm processors for the masses.

Next-gen 5 nanometer production will kick off next year, followed by mass production in late 2019 or early 2020. The company will invest as much as USD 25 billion in their new production facilities for this process node.

TSMC Breaks Ground on 5nm 'Fab 18' in Taiwan

TSMC today held a groundbreaking ceremony for its Fab 18, Phase 1 facility at the Southern Taiwan Science Park. Led by Chairman Dr. Morris Chang, the event demonstrates TSMC's ongoing commitment to investing in Taiwan as well as to environmental sustainability, and marks another milestone in TSMC's 30-year history and its competitive advantage in technology leadership, manufacturing excellence, and customer trust. TSMC's Fab 18 will be its fourth 12-inch GigaFab in Taiwan and is scheduled for production of the advanced 5 nanometer process.

Following today's groundbreaking, the Company plans to complete construction of Phase 1 and begin equipment move-in in the first quarter of 2019, with volume production in early 2020. Phase 2 will start construction in third quarter 2018 and also enter volume production in 2020, while Phase 3 construction is scheduled for third quarter 2019 for volume production in 2021. Once all three phases enter production, the facility's estimated annual capacity will exceed one million 12-inch wafers, providing 4,000 high-quality jobs and becoming another bastion of TSMC's manufacturing excellence.
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