Thursday, April 16th 2020

Huawei's Loss AMD's Gain, TSMC Develops Special 5nm Node

With Mainland Chinese tech giant Huawei being effectively cut off from contracting Taiwanese TSMC to manufacture its next-generation HiSilicon 5G mobile SoCs, and NVIDIA switching to Samsung for its next-generation GPUs, TSMC is looking to hold on to large high-volume customers besides Apple and Qualcomm, so as to not let them dictate pricing. AMD is at the receiving end of the newfound affection, with the semiconductor firm reportedly developing a new refinement of its 5 nm node specially for AMD, possibly to make Sunnyvale lock in on TSMC for its future chip architectures. A ChainNews report decoded by @chiakokhua sheds light on this development.

AMD is developing its "Zen 4" CPU microarchitecture for a 5 nm-class silicon fabrication node, although the company doesn't appear to have zeroed in on a node for its RDNA3 graphics architecture and CDNA2 scalar compute architecture. In its recent public reveal of the two, AMD chose not to specify the foundry node for the two, which come out roughly around the same time as "Zen 4." It wouldn't be far fetched to predict that AMD and TSMC were waiting on certainty for the new 5 nm-class node's development. There are no technical details of this new node. AMD's demand for TSMC is expected to be at least 20,000 12-inch wafers per month.
Sources: Chiakokhua (Twitter), ChainNews
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12 Comments on Huawei's Loss AMD's Gain, TSMC Develops Special 5nm Node

#3
R0H1T
Purely in terms of volumes AMD should be, if not not now then probably in 6 months time, the biggest volume customer for TSMC. With desktop, mobile, server, console chips & a tanking market for smartphones I can't see anyone making more chips/dies (off TSMC) than AMD ~ not even Apple.
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#4
mtcn77
btarunr
That report merely stated that AMD is TSMC's largest 7 nm-class customer after Apple transitioned to 5 nm-class on TSMC.
The thumbnail, "(DUV and EUV combined)" might infer 7nm and 5nm.
There must be some misnomer.
www.techpowerup.com/forums/threads/tsmc-unveils-6-nanometer-process.254660/
It says here;
TSMC's N6 process delivers 18% higher logic density over the N7 process. At the same time, its design rules are fully compatible with TSMC's proven N7 technology, allowing its comprehensive design ecosystem to be reused. As a result, it offers a seamless migration path with a fast design cycle time with very limited engineering resources for customers to achieve the product benefits from the new technology offering.
This isn't the citation I was willing to make, there was something about a free upgrade path. This could be the difference between 5nm new design necessitated vs. 6nm old design compatible.

Been on a goose chase.
N6

N6 is the EUV equivalent of N7. It is planned to use more EUV layers than N7+. It is both design rule and IP-compatible with N7 and is intended to be the main migration path for most customers. N7 designs may be taped out again on N6 leveraging EUV masks
...
This means it will ramp after N5. For that reason, TSMC says that N6 builds on both N7+ and N5 EUV learnings.
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#5
phanbuey
I just got a little excited.
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#6
TheGuruStud
Bye, bye, don't let the door hit ya on the way out, Huang.
Posted on Reply
#8
mtcn77
TheGuruStud
Bye, bye, don't let the door hit ya on the way out, Huang.
Samsung's gate all around might lower parasitic capacitance. This might be important in the effective tdp, since big chips leak more.
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#9
medi01
Console APUs alone means tens of million of 300mm2+ chips every year.
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#10
evernessince
Now AMD just needs to wrest control of OEMs from Intel's greedy clutches.
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#11
mtcn77
TSMC might have suffered some loss after a sudden turn of customer disinterest over the tablet craze. Local expert even calls it being incumbent upon AMD. Like what does he think AMD is moving volume...
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